loadpatents
name:-0.010977029800415
name:-0.012099981307983
name:-0.0027461051940918
Lin; Yi-Ruei Patent Filings

Lin; Yi-Ruei

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lin; Yi-Ruei.The latest application filed is for "interconnect arrangement with stress-reducing structure and method of fabricating the same".

Company Profile
1.8.8
  • Lin; Yi-Ruei - Taipei TW
  • LIN; Yi-Ruei - Taipei City TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Interconnect arrangement with stress-reducing structure and method of fabricating the same
Grant 10,204,843 - Lin , et al. Feb
2019-02-12
Semiconductor device with self-protecting fuse and method of fabricating the same
Grant 10,014,251 - Lai , et al. July 3, 2
2018-07-03
Interconnect Arrangement With Stress-reducing Structure And Method Of Fabricating The Same
App 20180076109 - LIN; Yi-Ruei ;   et al.
2018-03-15
Interconnect arrangement with stress-reducing structure and method of fabricating the same
Grant 9,818,666 - Lin , et al. November 14, 2
2017-11-14
Interconnect Arrangement With Stress-reducing Structure And Method Of Fabricating The Same
App 20170033030 - LIN; Yi-Ruei ;   et al.
2017-02-02
Interconnect arrangement with stress-reducing structure and method of fabricating the same
Grant 9,472,508 - Lin , et al. October 18, 2
2016-10-18
Semiconductor Device With Self-protecting Fuse And Method Of Fabricating The Same
App 20160190064 - LAI; Chen-Chung ;   et al.
2016-06-30
Interconnect Arrangement With Stress-reducing Structure And Method Of Fabricating The Same
App 20160118350 - LIN; Yi-Ruei ;   et al.
2016-04-28
Semiconductor device with self-protecting fuse and method of fabricating the same
Grant 9,299,658 - Lai , et al. March 29, 2
2016-03-29
Smart measurement techniques to enhance inline process control stability
Grant 9,299,621 - Yang , et al. March 29, 2
2016-03-29
Interconnect arrangement with stress-reducing structure and method of fabricating the same
Grant 9,252,047 - Lin , et al. February 2, 2
2016-02-02
Semiconductor Device With Self-protecting Fuse And Method Of Fabricating The Same
App 20150255394 - LAI; Chen-Chung ;   et al.
2015-09-10
Interconnect Arrangement With Stress-reducing Structure And Method Of Fabricating The Same
App 20150206845 - LIN; Yi-Ruei ;   et al.
2015-07-23
Semiconductor device with self-protecting fuse
Grant 9,070,687 - Lai , et al. June 30, 2
2015-06-30
Smart Measurement Techniques to Enhance Inline Process Control Stability
App 20150069395 - Yang; Han-Wei ;   et al.
2015-03-12
Semiconductor Device With Self-Protecting Fuse And Method Of Fabricating The Same
App 20150001592 - Lai; Chen-Chung ;   et al.
2015-01-01

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