Lin; Shen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lin; Shen.The latest application filed is for "compositions and methods for treatment of cystic fibrosis".

Company Profile

0.8.10

Lin; Shen - Philadelphia PA
Lin; Shen - Foster City CA
Lin; Shen - Gillette NJ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks

Patent Activity

Patent	Date
Compositions And Methods For Treatment Of Cystic Fibrosis App 20220241436 - Engelhardt; John F. ; et al.	2022-08-04
On-chip power-ground inductance modeling using effective self-loop-inductance Grant 6,981,230 - Lin , et al. December 27, 2	2005-12-27
System and method to reduce leakage power in an electronic device Grant 6,981,231 - Xie , et al. December 27, 2	2005-12-27
System and method for determining a plurality of clock delay values using an optimization algorithm Grant 6,925,555 - Chang , et al. August 2, 2	2005-08-02
Method for reducing current surge using multi-stage ramp shunting Grant 6,661,281 - Nakagawa , et al. December 9, 2	2003-12-09
Methods for full-chip vectorless dynamic IR analysis in IC designs App 20030212973 - Lin, Shen ; et al.	2003-11-13
Method for full-chip vectorless dynamic IR and timing impact analysis in IC designs App 20030212538 - Lin, Shen ; et al.	2003-11-13
Partial swing low power CMOS logic circuits Grant 6,621,305 - Nakagawa , et al. September 16, 2	2003-09-16
System and method to reduce leakage power in an electronic device App 20030163792 - Xie, Weize ; et al.	2003-08-28
Method for reducing current surge using multi-stage ramp shunting App 20030098742 - Nakagawa, Osamu Samuel ; et al.	2003-05-29
System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values Grant 6,567,960 - Chang , et al. May 20, 2	2003-05-20
System and method for predictive power ramping App 20030084353 - Chang, Norman ; et al.	2003-05-01
System for improving circuit simulations by utilizing a simplified circuit model based on effective capacitance and inductance values App 20030070148 - Chang, Norman ; et al.	2003-04-10
Partial swing low power CMOS logic circuits App 20030030467 - Nakagawa, Osamu Samuel ; et al.	2003-02-13
Parallel push algorithm detecting constraints to minimize clock skew App 20030020527 - Lin, Shen ; et al.	2003-01-30
Optimization of clock scheduling for a synchronous system App 20030023327 - Chang, Norman ; et al.	2003-01-30
Method for extracting inductance parameters from a circuit design Grant 6,434,724 - Chang , et al. August 13, 2	2002-08-13
Method Of Minimizing The Interconnection Cost Of Linked Objects Grant 3,617,714 - Kernighan , et al. November 2, 1	1971-11-02

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.