Lin; Ming-Ren

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lin; Ming-Ren.The latest application filed is for "double and triple gate mosfet devices and methods for making same".

Company Profile

0.88.23

Lin; Ming-Ren - Cupertino CA
Lin; Ming-Ren - Cupertio CA
Lin, Ming-Ren - Taipei-Hsien TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Double and triple gate MOSFET devices and methods for making same Grant 8,580,660 - Lin , et al. November 12, 2	2013-11-12
Strained fully depleted silicon on insulator semiconductor device Grant 8,502,283 - Xiang , et al. August 6, 2	2013-08-06
Method of forming finned semiconductor devices with trench isolation Grant 8,431,466 - Lin , et al. April 30, 2	2013-04-30
Double And Triple Gate Mosfet Devices And Methods For Making Same App 20120252193 - LIN; Ming-Ren ; et al.	2012-10-04
Double and triple gate MOSFET devices and methods for making same Grant 8,222,680 - Lin , et al. July 17, 2	2012-07-17
Method Of Forming Finned Semiconductor Devices With Trench Isolation App 20110263094 - LIN; Ming-ren ; et al.	2011-10-27
Fully silicided gate structure for FinFET devices Grant 8,008,136 - Lin , et al. August 30, 2	2011-08-30
Method of forming finned semiconductor devices with trench isolation Grant 7,994,020 - Lin , et al. August 9, 2	2011-08-09
Method of forming fin structures using a sacrificial etch stop layer on bulk semiconductor material Grant 7,871,873 - Maszara , et al. January 18, 2	2011-01-18
Method Of Forming Fin Structures Using A Sacrificial Etch Stop Layer On Bulk Semiconductor Material App 20100248454 - MASZARA; Witold ; et al.	2010-09-30
Method of forming isolation regions for integrated circuits Grant 7,713,834 - Wang , et al. May 11, 2	2010-05-11
Tensile strained substrate Grant 7,701,019 - Ngo , et al. April 20, 2	2010-04-20
Method Of Forming Finned Semiconductor Devices With Trench Isolation App 20100015778 - LIN; Ming-ren ; et al.	2010-01-21
Shallow trench isolation process Grant 7,648,886 - Ngo , et al. January 19, 2	2010-01-19
Reversed T-shaped finfet Grant 7,541,267 - Wang , et al. June 2, 2	2009-06-02
Systems and methods for forming multiple fin structures using metal-induced-crystallization Grant 7,498,225 - Wang , et al. March 3, 2	2009-03-03
Method Of Forming Isolation Regions For Integrated Circuits App 20090047770 - Wang; Haihong ; et al.	2009-02-19
Method of forming isolation regions for integrated circuits Grant 7,422,961 - Wang , et al. September 9, 2	2008-09-09
Doped structure for finfet devices Grant 7,416,925 - Lin , et al. August 26, 2	2008-08-26
Strained Fully Depleted Silicon On Insulator Semiconductor Device App 20080054316 - Xiang; Qi ; et al.	2008-03-06
Methods for fabricating a semiconductor device, which include selectively depositing an electrically conductive material Grant 7,329,582 - Pan , et al. February 12, 2	2008-02-12
Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor Grant 7,306,997 - Xiang , et al. December 11, 2	2007-12-11
Reversed T-shaped FinFET Grant 7,250,645 - Wang , et al. July 31, 2	2007-07-31
Heat removal in SOI devices using a buried oxide layer/conductive layer combination Grant 7,238,591 - Lin July 3, 2	2007-07-03
Method for doping structures in FinFET devices Grant 7,235,436 - Lin , et al. June 26, 2	2007-06-26
Doped Structure For Finfet Devices App 20070141791 - Lin; Ming-Ren ; et al.	2007-06-21
Flash memory device Grant 7,196,372 - Yu , et al. March 27, 2	2007-03-27
Doped structure for FinFET devices Grant 7,196,374 - Lin , et al. March 27, 2	2007-03-27
Fully Silicided Gate Structure For Finfet Devices App 20060177998 - Lin; Ming-Ren ; et al.	2006-08-10
Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same Grant 7,078,278 - Pan , et al. July 18, 2	2006-07-18
Tensile strained substrate App 20060138479 - Ngo; Minh V. ; et al.	2006-06-29
Method of forming merged FET inverter/logic gate Grant 7,064,022 - Hill , et al. June 20, 2	2006-06-20
Strained fully depleted silicon on insulator semiconductor device and manufacturing method therefor App 20060099752 - Xiang; Qi ; et al.	2006-05-11
Semiconductor with tensile strained substrate and method of making the same Grant 7,001,837 - Ngo , et al. February 21, 2	2006-02-21
Shallow trench isolation process using oxide deposition and anneal Grant 6,962,857 - Ngo , et al. November 8, 2	2005-11-08
Dual-metal CMOS transistors with tunable gate electrode work function and method of making the same App 20050245016 - Pan, James ; et al.	2005-11-03
Scribe lane for gettering of contaminants on SOI wafers and gettering method Grant 6,958,264 - Lin October 25, 2	2005-10-25
Semiconductor on insulator MOSFET having strained silicon channel Grant 6,943,087 - Xiang , et al. September 13, 2	2005-09-13
Strained silicon MOSFET having reduced leakage and method of its formation Grant 6,924,182 - Xiang , et al. August 2, 2	2005-08-02
Treatment of dielectric material to enhance etch rate Grant 6,905,971 - Tabery , et al. June 14, 2	2005-06-14
Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends Grant 6,893,929 - Xiang , et al. May 17, 2	2005-05-17
Depletion to avoid cross contamination Grant 6,858,503 - Ngo , et al. February 22, 2	2005-02-22
Damascene finfet gate with selective metal interdiffusion Grant 6,855,989 - Wang , et al. February 15, 2	2005-02-15
Self aligned double gate transistor having a strained channel region and process therefor Grant 6,855,982 - Xiang , et al. February 15, 2	2005-02-15
Method for forming structures in finfet devices Grant 6,852,576 - Lin , et al. February 8, 2	2005-02-08
Two transistor NOR device Grant 6,842,048 - Krivokapic , et al. January 11, 2	2005-01-11
Heat removal in SOI devices using a buried oxide layer/conductive layer combination Grant 6,833,587 - Lin December 21, 2	2004-12-21
Narrow fins by oxidation in double-gate finfet Grant 6,812,119 - Ahmed , et al. November 2, 2	2004-11-02
Method for forming structures in finfet devices App 20040198031 - Lin, Ming-Ren ; et al.	2004-10-07
FinFET device incorporating strained silicon in the channel region Grant 6,800,910 - Lin , et al. October 5, 2	2004-10-05
Shallow trench isolation for strained silicon processes App 20040180509 - Wang, Haihong ; et al.	2004-09-16
Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal Grant 6,790,782 - Yang , et al. September 14, 2	2004-09-14
Mosfets incorporating nickel germanosilicided gate and methods for their formation Grant 6,787,864 - Paton , et al. September 7, 2	2004-09-07
Semiconductor with tensile strained substrate and method of making the same App 20040142545 - Ngo, Minh V. ; et al.	2004-07-22
Implantation into high-K dielectric material after gate etch to facilitate removal Grant 6,764,898 - En , et al. July 20, 2	2004-07-20
Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric Grant 6,764,966 - En , et al. July 20, 2	2004-07-20
Shallow trench isolation for strained silicon processes App 20040137742 - Ngo, Minh-Van ; et al.	2004-07-15
FinFET device with multiple fin structures Grant 6,762,448 - Lin , et al. July 13, 2	2004-07-13
Two transistor nor device App 20040100306 - Krivokapic, Zoran ; et al.	2004-05-27
Double and triple gate MOSFET devices and methods for making same App 20040075122 - Lin, Ming-Ren ; et al.	2004-04-22
Finfet having improved carrier mobility and method of its formation App 20040061178 - Lin, Ming-Ren ; et al.	2004-04-01
Mosfets incorporating nickel germanosilicided gate and methods for their formation App 20040061191 - Paton, Eric N. ; et al.	2004-04-01
Transistor with local insulator structure Grant 6,670,260 - Yu , et al. December 30, 2	2003-12-30
Simplified fastening means App 20030215284 - Wang, Shyh-Jen ; et al.	2003-11-20
Fastening means Grant 6,619,878 - Wang , et al. September 16, 2	2003-09-16
Linerless shallow trench isolation method Grant 6,534,379 - Fisher , et al. March 18, 2	2003-03-18
Embedded conductor for SOI devices using a buried conductive layer/conductive plug combination Grant 6,531,753 - Lin March 11, 2	2003-03-11
High-K gate dielectric process with process with self aligned damascene contact to damascene gate and a low-k inter level dielectric Grant 6,492,249 - Xiang , et al. December 10, 2	2002-12-10
Through wafer backside contact to improve SOI heat dissipation Grant 6,483,147 - Lin November 19, 2	2002-11-19
Fastening means App 20020131818 - Wang, Shyh-Jen ; et al.	2002-09-19
Method of manufacturing a transistor with local insulator structure Grant 6,380,019 - Yu , et al. April 30, 2	2002-04-30
Low resistance composite contact structure utilizing a reaction barrier layer under a metal layer Grant 6,369,429 - Pramanick , et al. April 9, 2	2002-04-09
High-k Gate Dielectric Process With Self Aligned Damascene Contact To Damascene Gate And A Low-k Inter Level Dielectric App 20010053594 - XIANG, QI ; et al.	2001-12-20
Method Of Gate Doping By Ion Implantation App 20010030349 - LIN, MING-REN ; et al.	2001-10-18
Method of forming transistors with self aligned damascene gate contact Grant 6,291,278 - Xiang , et al. September 18, 2	2001-09-18
Integrated circuit having isolation structures Grant 6,281,555 - Yu , et al. August 28, 2	2001-08-28
Integrated circuit having transistors with different threshold voltages Grant 6,262,456 - Yu , et al. July 17, 2	2001-07-17
Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant using lowered temperatures Grant 6,248,675 - Xiang , et al. June 19, 2	2001-06-19
MOS transistor with stepped gate insulator Grant 6,225,661 - An , et al. May 1, 2	2001-05-01
Method of forming multiple levels of patterned metallization Grant 6,207,553 - Buynoski , et al. March 27, 2	2001-03-27
Method for fabricating a MOSFET device structure which facilitates mitigation of junction capacitance and floating body effects Grant 6,204,138 - Krishnan , et al. March 20, 2	2001-03-20
Method of fabricating an integrated circuit with ultra-shallow source/drain extensions Grant 6,200,869 - Yu , et al. March 13, 2	2001-03-13
Electron bean curing of low-k dielectrics in integrated circuits Grant 6,169,039 - Lin , et al. January 2, 2	2001-01-02
Fabrication of field effect transistors having dual gates with gate dielectrics of high dielectric constant Grant 6,159,782 - Xiang , et al. December 12, 2	2000-12-12
Method of forming asymmetrically doped source/drain regions Grant 6,140,186 - Lin , et al. October 31, 2	2000-10-31
CMOS optimization method utilizing sacrificial sidewall spacer Grant 6,093,594 - Yeap , et al. July 25, 2	2000-07-25
Fabrication of dual gates of field transistors with prevention of reaction between the gate electrode and the gate dielectric with a high dielectric constant Grant 6,087,231 - Xiang , et al. July 11, 2	2000-07-11
Method of producing a metal oxide semiconductor device with raised source/drain Grant 6,083,798 - Lin July 4, 2	2000-07-04
Transistor with local insulator structure Grant 6,084,271 - Yu , et al. July 4, 2	2000-07-04
Damascene process for reduced feature size Grant 6,077,773 - Lin June 20, 2	2000-06-20
Fast Mosfet with low-doped source/drain Grant 6,060,364 - Maszara , et al. May 9, 2	2000-05-09
High quality isolation for high density and high performance integrated circuits Grant 5,972,773 - Liu , et al. October 26, 1	1999-10-26
Suppression of boron segregation for shallow source and drain junctions in semiconductors Grant 5,960,322 - Xiang , et al. September 28, 1	1999-09-28
Self-aligned silicide gate technology for advanced submicron MOS devices Grant 5,937,315 - Xiang , et al. August 10, 1	1999-08-10
Method for producing semiconductor devices with small contacts, vias, or damascene trenches Grant 5,893,748 - Lin April 13, 1	1999-04-13
Method of manufacturing a polysilicon gate having a dimension below the photolithography limitation Grant 5,866,473 - Xiang , et al. February 2, 1	1999-02-02
Method for producing ultra-fine interconnection features Grant 5,863,707 - Lin January 26, 1	1999-01-26
Self aligned via dual damascene Grant 5,795,823 - Avanzino , et al. August 18, 1	1998-08-18
Advanced copper interconnect system that is compatible with existing IC wire bonding technology Grant 5,785,236 - Cheung , et al. July 28, 1	1998-07-28
Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device Grant 5,770,519 - Klein , et al. June 23, 1	1998-06-23
Damascene process for reduced feature size Grant 5,753,967 - Lin May 19, 1	1998-05-19
Dual damascene with a sacrificial via fill Grant 5,705,430 - Avanzino , et al. January 6, 1	1998-01-06
Subtractive dual damascene Grant 5,691,238 - Avanzino , et al. November 25, 1	1997-11-25
Dual damascene with a protective mask for via etching Grant 5,686,354 - Avanzino , et al. November 11, 1	1997-11-11
Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device Grant 5,646,448 - Klein , et al. July 8, 1	1997-07-08
Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device Grant 5,639,691 - Klein , et al. June 17, 1	1997-06-17
Simplified dual damascene process for multi-level metallization and interconnection structure Grant 5,635,423 - Huang , et al. June 3, 1	1997-06-03
Self aligned via dual damascene Grant 5,614,765 - Avanzino , et al. March 25, 1	1997-03-25

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