Lin; Jyh Rong

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lin; Jyh Rong.The latest application filed is for "chip package structure".

Company Profile

5.19.20

Lin; Jyh Rong - Zhubei TW
LIN; Jyh Rong - Taiwan CN
Lin; Jyh Rong - Hsinchu TW
Lin; Jyh Rong - Zhubei City TW
Lin; Jyh-Rong - Tucheng TW
Lin; Jyh-Rong - Tucheng City TW
Lin; Jyh-Rong - Taipei TW
Lin; Jyh-Rong - Tu-Cheng TW
Lin, Jyh-Rong - Tu-Cheng City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatus and manufacturing method Grant 10,784,181 - Fu , et al. Sept	2020-09-22
Chip Package Structure App 20200135615 - FU; HuiLi ; et al.	2020-04-30
Packaged chip and signal transmission method based on packaged chip Grant 10,490,506 - Ma , et al. Nov	2019-11-26
Chip Grant 10,475,741 - Fu , et al. Nov	2019-11-12
Semiconductor Apparatus And Manufacturing Method Thereof App 20190198422 - LIN; Jyh Rong ; et al.	2019-06-27
Packaged Chip and Signal Transmission Method Based on Packaged Chip App 20180190590 - Ma; Chih Chiang ; et al.	2018-07-05
Apparatus and Manufacturing Method App 20180190566 - Fu; HuiLi ; et al.	2018-07-05
Chip App 20180025973 - Fu; HuiLi ; et al.	2018-01-25
Electrically stackable semiconductor wafer and chip packages Grant 9,601,474 - Chen , et al. March 21, 2	2017-03-21
Wafer Leveled Chip Packaging Structure and Method Thereof App 20150364457 - Chen; Shou-Lung ; et al.	2015-12-17
Wafer leveled chip packaging structure and method thereof Grant 9,059,181 - Chen , et al. June 16, 2	2015-06-16
Wafer Leveled Chip Packaging Structure and Method Thereof App 20140217587 - Chen; Shou-Lung ; et al.	2014-08-07
Wafer-leveled chip packaging structure and method thereof Grant 8,587,091 - Chen , et al. November 19, 2	2013-11-19
Semiconductor package device Grant 8,314,482 - Chen , et al. November 20, 2	2012-11-20
Wafer-leveled Chip Packaging Structure And Method Thereof App 20120267765 - CHEN; Shou-Lung ; et al.	2012-10-25
Semiconductor package and method of manufacturing the same Grant 8,248,803 - Lin , et al. August 21, 2	2012-08-21
Semiconductor Package And Method Of Manufacturing The Same App 20110242765 - LIN; Jyh-Rong ; et al.	2011-10-06
Substrate warpage-reducing structure Grant 7,879,438 - Lin , et al. February 1, 2	2011-02-01
Electronic device package and method of manufacturing the same Grant 7,838,333 - Chen , et al. November 23, 2	2010-11-23
Substrate Warpage-reducing Structure App 20100247879 - Lin; Jyh-Rong ; et al.	2010-09-30
Electronic Device Package And Method Of Manufacturing The Same App 20100112757 - CHEN; Shou-Lung ; et al.	2010-05-06
Electronic device package and method of manufacturing the same Grant 7,632,707 - Chen , et al. December 15, 2	2009-12-15
Packaging structure and method of an image sensor module Grant 7,572,676 - Leu , et al. August 11, 2	2009-08-11
Electronic Circuit Package App 20090115051 - Leung; Lap-Wai Lydia ; et al.	2009-05-07
Wafer-leveled chip packaging structure and method thereof Grant 7,528,009 - Chen , et al. May 5, 2	2009-05-05
Packaging structure and method of an image sensor module Grant 7,411,306 - Leu , et al. August 12, 2	2008-08-12
Wafer-leveled chip packaging structure and method thereof App 20080029870 - Chen; Shou-Lung ; et al.	2008-02-07
Wafer-leveled chip packaging structure and method thereof Grant 7,294,920 - Chen , et al. November 13, 2	2007-11-13
Packaging structure and method of an image sensor module App 20070195188 - Leu; Fang-Jun ; et al.	2007-08-23
Wafer-leveled chip packaging structure and method thereof App 20070197018 - Chen; Shou-Lung ; et al.	2007-08-23
Electronic device package and method of manufacturing the same App 20060157864 - Chen; Shou-Lung ; et al.	2006-07-20
Packaging structure and method of an image sensor module App 20060030070 - Leu; Fang-Jun ; et al.	2006-02-09
Wafer-leveled chip packaging structure and method thereof App 20060019484 - Chen; Shou-Lung ; et al.	2006-01-26
Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed Grant 6,605,525 - Lu , et al. August 12, 2	2003-08-12
Structure of the metal bumping on the input/output connector of a substrate or wafer and method for manufacturing the same App 20030107132 - Chiang, Pang-Ming ; et al.	2003-06-12
Method for forming a wafer level package incorporating a multiplicity of elastomeric blocks and package formed App 20020164840 - Lu, Szu-Wei ; et al.	2002-11-07
Wafer level package incorporating elastomeric pads in dummy plugs Grant 6,358,836 - Lu , et al. March 19, 2	2002-03-19
Wafer level packaging method and packages formed Grant 6,277,669 - Kung , et al. August 21, 2	2001-08-21

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