Lin; Ji-Cheng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lin; Ji-Cheng.The latest application filed is for "stacked chip package structure and manufacturing method thereof".

Company Profile

6.10.11

Lin; Ji-Cheng - Hsinchu County TW
Lin; Ji-Cheng - Hsinchu TW
Lin; Ji-Cheng - Sinjhuang TW
Lin; Ji-Cheng - Taipei County TW
Lin; Ji-Cheng - HsinChung TW
Lin; Ji-Cheng - Sinjhuang City TW
Lin, Ji-cheng - Hsin Chu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stacked chip package structure and manufacturing method thereof Grant 10,950,557 - Fang , et al. March 16, 2	2021-03-16
Stacked Chip Package Structure And Manufacturing Method Thereof App 20200176395 - Fang; Li-Chih ; et al.	2020-06-04
Package structure and chip structure Grant 10,607,860 - Chiang , et al.	2020-03-31
Manufacturing method of package structure having conductive shield Grant 10,276,510 - Chiang , et al.	2019-04-30
Package Structure And Chip Structure App 20190096699 - Chiang; Chia-Wei ; et al.	2019-03-28
Manufacturing Method Of Package Structure App 20190096821 - Chiang; Chia-Wei ; et al.	2019-03-28
Stacked chip package structure and manufacturing method thereof Grant 9,825,010 - Fang , et al. November 21, 2	2017-11-21
Stacked Chip Package Structure And Manufacturing Method Thereof App 20170287870 - Fang; Li-Chih ; et al.	2017-10-05
Stacked Chip Package Structure And Manufacturing Method Thereof App 20170287874 - Fang; Li-Chih ; et al.	2017-10-05
Structure for reducing stress for vias and fabricating method thereof Grant 7,754,599 - Hsu , et al. July 13, 2	2010-07-13
Structure for protecting electronic packaging contacts from stress Grant 7,732,928 - Chang , et al. June 8, 2	2010-06-08
Mold array process for semiconductor packages Grant 7,691,676 - Fan , et al. April 6, 2	2010-04-06
Structure for reducing stress for vias and fabricating method thereof App 20090156001 - Hsu; Yung-Yu ; et al.	2009-06-18
Structure for reducing stress for vias and fabricating method thereof Grant 7,545,039 - Hsu , et al. June 9, 2	2009-06-09
Package structure for electronic device Grant 7,531,900 - Lin , et al. May 12, 2	2009-05-12
Composite bump Grant 7,378,746 - Lin , et al. May 27, 2	2008-05-27
Composite Bump App 20070210457 - Lin; Ji-Cheng ; et al.	2007-09-13
Package Structure For Electronic Device App 20070210429 - Lin; Ji-Cheng ; et al.	2007-09-13
Structure for reducing stress for vias and fabricating method thereof App 20070108572 - Hsu; Yung-Yu ; et al.	2007-05-17
Protecting structure and manufacturing method for electronic packaging contacts App 20070096279 - Chang; Shyh-Ming ; et al.	2007-05-03
Silicon Pressure Micro-sensing Device And The Fabrication Process App 20030068838 - Shie, Jin-shown ; et al.	2003-04-10

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.