Lin; Dahcheng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lin; Dahcheng.The latest application filed is for "low temperature mim capacitor for mixed-signal/rf applications".

Company Profile

0.10.2

Lin; Dahcheng - Kaohsiung TW
LIN, DAHCHENG - HSINCHU TW
Lin; Dahcheng - Hsin-Chu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Low temperature MIM capacitor for mixed-signal/RF applications Grant 6,822,283 - Lin , et al. November 23, 2	2004-11-23
Low temperature MIM capacitor for mixed-signal/RF applications App 20040009646 - Lin, Dahcheng ; et al.	2004-01-15
Method For Reducing Contact Resistance App 20010001495 - LIN, DAHCHENG ; et al.	2001-05-24
Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure Grant 6,194,265 - Chang , et al. February 27, 2	2001-02-27
Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer Grant 6,165,830 - Lin , et al. December 26, 2	2000-12-26
In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application Grant 6,127,221 - Lin , et al. October 3, 2	2000-10-03
Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications Grant 6,046,083 - Lin , et al. April 4, 2	2000-04-04
Process to reduce defect formation occurring during shallow trench isolation formation Grant 6,037,238 - Chang , et al. March 14, 2	2000-03-14
One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications Grant 6,037,219 - Lin , et al. March 14, 2	2000-03-14
Method for fabricating a stacked, or crown shaped, capacitor structure Grant 5,930,625 - Lin , et al. July 27, 1	1999-07-27
Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure Grant 5,913,119 - Lin , et al. June 15, 1	1999-06-15
Method of manufacturing hemispherical grained polysilicon with improved adhesion and reduced capacitance depletion Grant 5,897,352 - Lin , et al. April 27, 1	1999-04-27

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