Lin; Ching-San

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lin; Ching-San.The latest application filed is for "chip structure, chip bonding structure using the same, and manufacturing method thereof".

Company Profile

2.12.13

Lin; Ching-San - Taichung TW
- Wufeng Township, Taichung County TW
Lin; Ching-San - Wufeng Township, Taichung County N/A TW
Lin; Ching-San - Wufeng Township TW
Lin; Ching-San - Taichung County TW
Lin; Ching-San - Wufong Township Taichung County TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of metal sputtering for integrated circuit metal routing Grant 8,723,322 - Liu , et al. May 13, 2	2014-05-13
Integrated circuit wafer dicing method Grant 08617963 -	2013-12-31
Integrated circuit wafer dicing method Grant 8,617,963 - Lin , et al. December 31, 2	2013-12-31
Chip Structure, Chip Bonding Structure Using The Same, And Manufacturing Method Thereof App 20130249086 - Lin; Ching-San	2013-09-26
Die structure and die connecting method Grant 8,518,743 - Hsu , et al. August 27, 2	2013-08-27
Semiconductor chip with post-passivation scheme formed over passivation layer Grant 8,319,354 - Lin , et al. November 27, 2	2012-11-27
Semiconductor chip with passivation layer comprising metal interconnect and contact pads Grant 8,242,601 - Chou , et al. August 14, 2	2012-08-14
Semiconductor Structure And Manufacturing Method Thereof App 20120018880 - Wu; Kun-Tai ; et al.	2012-01-26
Integrated Circuit Wafer Dicing Method App 20120003817 - Lin; Ching-San ; et al.	2012-01-05
Semiconductor Chip With Post-passivation Scheme Formed Over Passivation Layer App 20110266669 - Chou; Chiu-Ming ; et al.	2011-11-03
Die Structure And Die Connecting Method App 20110254153 - Hsu; Chia-Hung ; et al.	2011-10-20
Chip Structure, Chip Bonding Structure Using The Same, And Manufacturing Method Thereof App 20110254152 - Lin; Ching-San	2011-10-20
Semiconductor chip with post-passivation scheme formed over passivation layer Grant 8,004,092 - Lin , et al. August 23, 2	2011-08-23
Semiconductor Chip with Passivation Layer Comprising Metal Interconnect and Contact Pads App 20090218687 - Chou; Chiu-Ming ; et al.	2009-09-03
Semiconductor chip with passivation layer comprising metal interconnect and contact pads Grant 7,547,969 - Chou , et al. June 16, 2	2009-06-16
Semiconductor Chip With Post-passivation Scheme Formed Over Passivation Layer App 20080265413 - Chou; Chiu-Ming ; et al.	2008-10-30
Semiconductor chip with post-passivation scheme formed over passivation layer Grant 7,397,121 - Chou , et al. July 8, 2	2008-07-08
Semiconductor chip with post-passivation scheme formed over passivation layer App 20070096313 - Chou; Chiu-Ming ; et al.	2007-05-03
Method of metal sputtering for integrated circuit metal routing App 20060148247 - Liu; Hsien-Tsung ; et al.	2006-07-06
Semiconductor chip with post-passivation scheme formed over passivation layer App 20060091540 - Chou; Chiu-Ming ; et al.	2006-05-04
Method of metal sputtering for integrated circuit metal routing App 20050040033 - Liu, Hsien-Tsung ; et al.	2005-02-24
Method of metal sputtering for integrated circuit metal routing Grant 6,802,945 - Liu , et al. October 12, 2	2004-10-12
Method of metal sputtering for integrated circuit metal routing App 20040129558 - Liu, Hsien-Tsung ; et al.	2004-07-08

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