| Patent | Date |
|---|
Slot Designs In Wide Metal Lines
App 20160233157 - LIM; Yeow Kheng ; et al. | 2016-08-11 |
Slot designs in wide metal lines
Grant 9,318,378 - Lim , et al. April 19, 2 | 2016-04-19 |
Dielectric posts in metal layers
Grant 8,957,523 - Zhang , et al. February 17, 2 | 2015-02-17 |
Crack-arresting structure for through-silicon vias
Grant 8,860,185 - Yuan , et al. October 14, 2 | 2014-10-14 |
Device With Integrated Passive Component
App 20140264733 - YUAN; Shaoning ; et al. | 2014-09-18 |
Dielectric Posts In Metal Layers
App 20140191407 - ZHANG; Fan ; et al. | 2014-07-10 |
Integrated circuit with self-aligned line and via
Grant 8,766,454 - Lim , et al. July 1, 2 | 2014-07-01 |
Back-side MOM/MIM devices
Grant 8,759,947 - Tan , et al. June 24, 2 | 2014-06-24 |
Device with integrated power supply
Grant 8,716,856 - Tan , et al. May 6, 2 | 2014-05-06 |
Device With Integrated Power Supply
App 20140035155 - TAN; Juan Boon ; et al. | 2014-02-06 |
Method For Forming Heat Sink With Through Silicon Vias
App 20130277810 - Tan; Juan Boon ; et al. | 2013-10-24 |
Back-side Mom/mim Devices
App 20130256834 - TAN; Juan Boon ; et al. | 2013-10-03 |
Crack-Arresting Structure for Through-Silicon Vias
App 20130187280 - Yuan; Shaoning ; et al. | 2013-07-25 |
TSV backside processing using copper damascene interconnect technology
Grant 8,466,062 - Lu , et al. June 18, 2 | 2013-06-18 |
TSV Backside Processing Using Copper Damascene Interconnect Technology
App 20130105968 - Lu; Yue Kang ; et al. | 2013-05-02 |
Integrated circuit system employing low-k dielectrics and method of manufacture thereof
Grant 8,358,007 - Sohn , et al. January 22, 2 | 2013-01-22 |
Integrated Circuit System Employing Low-k Dielectrics And Method Of Manufacture Thereof
App 20100314763 - Sohn; Dong Kyun ; et al. | 2010-12-16 |
Formation of metal silicide layer over copper interconnect for reliability enhancement
Grant 7,790,617 - Lim , et al. September 7, 2 | 2010-09-07 |
Method to fabricate aligned dual damascene openings
Grant 7,372,156 - Lim , et al. May 13, 2 | 2008-05-13 |
Integrated circuit system using dual damascene process
Grant 7,253,097 - Lim , et al. August 7, 2 | 2007-08-07 |
Formation of metal silicide layer over copper interconnect for reliability enhancement
App 20070111522 - Lim; Yeow Kheng ; et al. | 2007-05-17 |
Integrated Circuit With Self-aligned Line And Via
App 20070075371 - Lim; Yeow Kheng ; et al. | 2007-04-05 |
Integrated Circuit System Using Dual Damascene Process
App 20070001303 - Lim; Yeow Kheng ; et al. | 2007-01-04 |
Integrated circuit with self-aligned line and via and manufacturing method therefor
Grant 7,119,010 - Lim , et al. October 10, 2 | 2006-10-10 |
Slot designs in wide metal lines
App 20060040491 - Lim; Yeow Kheng ; et al. | 2006-02-23 |
Method to fabricate aligned dual damacene openings
App 20060003573 - Lim; Yeow Kheng ; et al. | 2006-01-05 |
Method to fabricate aligned dual damascene openings
Grant 6,967,156 - Lim , et al. November 22, 2 | 2005-11-22 |
Method to fabricate aligned dual damascene openings
App 20050090095 - Lim, Yeow Kheng ; et al. | 2005-04-28 |
Dual silicon-on-insulator device wafer die
Grant 6,849,928 - Cha , et al. February 1, 2 | 2005-02-01 |
Method to fabricate elevated source/drain transistor with large area for silicidation
Grant 6,780,691 - Cha , et al. August 24, 2 | 2004-08-24 |
Method to fabricate elevated source/drain transistor with large area for silicidation
App 20040033668 - Cha, Randall Cher Liang ; et al. | 2004-02-19 |
Integrated circuit with self-aligned line and via and manufacturing method therefor
App 20030197279 - Lim, Yeow Kheng ; et al. | 2003-10-23 |
Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance
Grant 6,613,652 - Lim , et al. September 2, 2 | 2003-09-02 |
Dual silicon-on-insulator device wafer die
App 20030107083 - Cha, Randall Cher Liang ; et al. | 2003-06-12 |
Dual silicon-on-insulator device wafer die
Grant 6,558,994 - Cha , et al. May 6, 2 | 2003-05-06 |
Method for fabricating SOI devices with option of incorporating air-gap feature for better insulation and performance
App 20020132448 - Lim, Yeow Kheng ; et al. | 2002-09-19 |
Dual silicon-on-insulator device wafer die
App 20020127816 - Cha, Randall Cher Liang ; et al. | 2002-09-12 |
Assorted aluminum wiring design to enhance chip-level performance for deep sub-micron application
App 20020127834 - Lim, Yeow Kheng ; et al. | 2002-09-12 |
Simplified Method To Reduce Or Eliminate Sti Oxide Divots
App 20020098661 - Cha, Randall Cher Liang ; et al. | 2002-07-25 |
Method to form high performance copper damascene interconnects by de-coupling via and metal line filling
Grant 6,380,084 - Lim , et al. April 30, 2 | 2002-04-30 |
Versatile copper-wiring layout design with low-k dielectric integration
Grant 6,355,563 - Cha , et al. March 12, 2 | 2002-03-12 |
Method to eliminate top metal corner shaping during bottom metal patterning for MIM capacitors via plasma ashing and hard masking technique
Grant 6,319,767 - Cha , et al. November 20, 2 | 2001-11-20 |
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