Lim; Sin Leng
Patent Applications and Registrations
Patent applications and USPTO patent grants for Lim; Sin Leng.The latest application filed is for "planarized passivation layer for semiconductor devices".
- Lim; Sin Leng - Singapore SG
| Patent | Date |
|---|---|
| Planarized passivation layer for semiconductor devices Grant 8,264,088 - Lim , et al. September 11, 2 | 2012-09-11 |
| Planarized Passivation Layer For Semiconductor Devices App 20110266688 - LIM; Sin Leng ; et al. | 2011-11-03 |
| Planarized passivation layer for semiconductor devices Grant 7,998,831 - Lim , et al. August 16, 2 | 2011-08-16 |
| Integrated circuit having ultralow-K dielectric layer Grant 7,829,422 - Widodo , et al. November 9, 2 | 2010-11-09 |
| Planarized Passivation Layer For Semiconductor Devices App 20080246159 - LIM; Sin Leng ; et al. | 2008-10-09 |
| Integrated Circuit Having Ultralow-K Dielectric Layer App 20080153310 - Widodo; Johnny ; et al. | 2008-06-26 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 