Lim; Eng Hua

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lim; Eng Hua.The latest application filed is for "double anneal with improved reliability for dual contact etch stop liner scheme".

Company Profile

0.21.14

Lim; Eng Hua - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Double anneal with improved reliability for dual contact etch stop liner scheme Grant 8,148,221 - Lim , et al. April 3, 2	2012-04-03
Double Anneal with Improved Reliability for Dual Contact Etch Stop Liner Scheme App 20100041242 - LIM; Khee Yong ; et al.	2010-02-18
Double anneal with improved reliability for dual contact etch stop liner scheme Grant 7,615,433 - Lim , et al. November 10, 2	2009-11-10
Method and structure for forming strained devices Grant 7,545,004 - Yang , et al. June 9, 2	2009-06-09
Structure and method to implement dual stressor layers with improved silicide control App 20080026523 - Lee; Yong Meng ; et al.	2008-01-31
Double anneal with improved reliability for dual contact etch stop liner scheme App 20070138564 - Lim; Khee Yong ; et al.	2007-06-21
Method And Structure For Forming Strained Devices App 20060228836 - Yang; Haining S. ; et al.	2006-10-12
Method And Structure For Improving Cmos Device Reliability Using Combinations Of Insulating Materials App 20060079046 - Yang; Haining ; et al.	2006-04-13
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing App 20050101083 - Ang, Chew Hoe ; et al.	2005-05-12
Method to pattern small features by using a re-flowable hard mask App 20050089777 - Ang, Chew-Hoe ; et al.	2005-04-28
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing Grant 6,841,441 - Ang , et al. January 11, 2	2005-01-11
Formation of small gates beyond lithographic limits App 20040266155 - Ang, Chew Hoe ; et al.	2004-12-30
Method to pattern small features by using a re-flowable hard mask Grant 6,828,082 - Ang , et al. December 7, 2	2004-12-07
Method of forming a high performance and low cost CMOS device Grant 6,762,085 - Zheng , et al. July 13, 2	2004-07-13
Method to produce dual gates (one metal and one poly or metal silicide) for CMOS devices using sputtered metal deposition, metallic ion implantation, or silicon implantation, and laser annealing App 20040132271 - Ang, Chew Hoe ; et al.	2004-07-08
Method of forming a high performance and low cost CMOS device App 20040063264 - Zheng, Jia Zhen ; et al.	2004-04-01
Method for forming L-shaped spacers with precise width control Grant 6,664,156 - Ang , et al. December 16, 2	2003-12-16
Method to fabricate a single gate with dual work-functions Grant 6,664,153 - Ang , et al. December 16, 2	2003-12-16
Method of cobalt silicidation using an oxide-Titanium interlayer Grant 6,653,227 - Lai , et al. November 25, 2	2003-11-25
Method of fabricating variable length vertical transistors Grant 6,632,712 - Ang , et al. October 14, 2	2003-10-14
Method of forming almost L-shaped spacer for improved ILD gap fill Grant 6,632,745 - Yap , et al. October 14, 2	2003-10-14
Forming dual gate oxide thickness on vertical transistors by ion implantation Grant 6,610,575 - Ang , et al. August 26, 2	2003-08-26
Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask Grant 6,610,604 - Ang , et al. August 26, 2	2003-08-26
Method to fabricate a single gate with dual work-functions App 20030153139 - Ang, Chew Hoe ; et al.	2003-08-14
Method to pattern small features by using a re-flowable hard mask App 20030152871 - Ang, Chew-Hoe ; et al.	2003-08-14
Method of fabricating CMOS device with dual gate electrode Grant 6,605,501 - Ang , et al. August 12, 2	2003-08-12
Method Of Forming Small Transistor Gates By Using Self-aligned Reverse Spacer As A Hard Mask App 20030148617 - Ang, Chew-Hoe ; et al.	2003-08-07
Method to form high k dielectric and silicide to reduce poly depletion by using a sacrificial metal between oxide and gate Grant 6,429,109 - Zheng , et al. August 6, 2	2002-08-06
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts Grant 6,350,661 - Lim , et al. February 26, 2	2002-02-26
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts App 20010031540 - Lim, Chong Wee ; et al.	2001-10-18
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts Grant 6,297,126 - Lim , et al. October 2, 2	2001-10-02
Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication Grant 6,271,133 - Lim , et al. August 7, 2	2001-08-07
Partially recessed shallow trench isolation method for fabricating borderless contacts Grant 6,265,302 - Lim , et al. July 24, 2	2001-07-24
Method to form shallow trench isolations with rounded corners and reduced trench oxide recess Grant 6,228,727 - Lim , et al. May 8, 2	2001-05-08
Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device Grant 6,165,871 - Lim , et al. December 26, 2	2000-12-26

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