Lim; Chong Wee

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lim; Chong Wee.The latest application filed is for "method for forming a strained semiconductor substrate".

Company Profile

0.10.5

Lim; Chong Wee - Urbana IL
Lim; Chong Wee - Misia MY
Lim; Chong Wee - J.B. MY
Lim; Chong Wee - Johor Bahru MY
Lim; Chong Wee - Tmn. Century MY
Lim; Chong Wee - Singapore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Epitaxial CoSi2 on MOS devices Grant 6,846,359 - Lim , et al. January 25, 2	2005-01-25
Method for forming a strained semiconductor substrate App 20040224469 - Lim, Chong Wee ; et al.	2004-11-11
Method for forming an epitaxial cobalt silicide layer on MOS devices Grant 6,797,598 - Lim , et al. September 28, 2	2004-09-28
Method for large-scale fabrication of atomic-scale structures on material surfaces using surface vacancies Grant 6,762,131 - Lim , et al. July 13, 2	2004-07-13
Epitaxial CoSi2 on MOS devices App 20040079279 - Lim, Chong Wee ; et al.	2004-04-29
Method for forming an epitaxial cobalt silicide layer on MOS devices App 20040038528 - Lim, Chong Wee ; et al.	2004-02-26
Method for large-scale fabrication of atomic-scale structures on material surfaces using surface vacancies App 20030194875 - Lim, Chong Wee ; et al.	2003-10-16
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts Grant 6,350,661 - Lim , et al. February 26, 2	2002-02-26
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts App 20010031540 - Lim, Chong Wee ; et al.	2001-10-18
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts Grant 6,297,126 - Lim , et al. October 2, 2	2001-10-02
Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication Grant 6,271,133 - Lim , et al. August 7, 2	2001-08-07
Partially recessed shallow trench isolation method for fabricating borderless contacts Grant 6,265,302 - Lim , et al. July 24, 2	2001-07-24
Method to form shallow trench isolations with rounded corners and reduced trench oxide recess Grant 6,228,727 - Lim , et al. May 8, 2	2001-05-08
Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device Grant 6,165,871 - Lim , et al. December 26, 2	2000-12-26
Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application Grant 6,093,628 - Lim , et al. July 25, 2	2000-07-25

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.