LILES; Stephen Edward

Patent Applications and Registrations

Patent applications and USPTO patent grants for LILES; Stephen Edward.The latest application filed is for "voltage aware circuit for dual voltage domain signals".

Company Profile

0.14.10

LILES; Stephen Edward - Apex NC

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Voltage Aware Circuit For Dual Voltage Domain Signals App 20180152176 - GE; Shaoping ; et al.	2018-05-31
Write bitline driver for a dual voltage domain Grant 9,911,472 - Ge , et al. March 6, 2	2018-03-06
Voltage level shifters employing preconditioning circuits, and related systems and methods Grant 9,768,779 - Nadkarni , et al. September 19, 2	2017-09-19
Efficient compare operation Grant 9,640,250 - Hoff , et al. May 2, 2	2017-05-02
Dynamic voltage level shifters employing pulse generation circuits, and related systems and methods Grant 9,608,637 - Chai , et al. March 28, 2	2017-03-28
Dynamic Voltage Level Shifters Employing Pulse Generation Circuits, And Related Systems And Methods App 20170047930 - Chai; Chiaming ; et al.	2017-02-16
Pipelining an asynchronous memory reusing a sense amp and an output latch Grant 9,548,089 - Liles , et al. January 17, 2	2017-01-17
Voltage Level Shifters Employing Preconditioning Circuits, And Related Systems And Methods App 20160359487 - Nadkarni; Rahul Krishnakumar ; et al.	2016-12-08
Pipelining An Asynchronous Memory Reusing A Sense Amp And An Output Latch App 20160293234 - LILES; Stephen Edward ; et al.	2016-10-06
Redirecting data from a defective data entry in memory to a redundant data entry prior to data access, and related systems and methods Grant 9,442,675 - Chai , et al. September 13, 2	2016-09-13
Voltage level shifted self-clocked write assistance Grant 9,378,789 - Hoff , et al. June 28, 2	2016-06-28
Voltage Level Shifted Self-clocked Write Assistance App 20160093346 - HOFF; David Paul ; et al.	2016-03-31
Static random access memory (SRAM) global bitline circuits for reducing power glitches during memory read accesses, and related methods and systems Grant 9,019,752 - Puckett , et al. April 28, 2	2015-04-28
Pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power, and related systems and methods Grant 9,007,817 - Chai , et al. April 14, 2	2015-04-14
Pre-charging Bitlines In A Static Random Access Memory (sram) Prior To Data Access For Reducing Leakage Power, And Related Systems And Methods App 20140328113 - Chai; Chiaming ; et al.	2014-11-06
Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width Grant 8,638,153 - Ge , et al. January 28, 2	2014-01-28
Pulse Clock Generation Logic with Built-in Level Shifter and Programmable Rising Edge and Pulse Width App 20130257498 - Ge; Shaoping ; et al.	2013-10-03
Circuits, systems, and methods for dynamic voltage level shifting Grant 8,456,929 - Liles , et al. June 4, 2	2013-06-04
Circuits, Systems, and Methods for Dynamic Voltage Level Shifting App 20110249518 - Liles; Stephen Edward ; et al.	2011-10-13
Self-tuning of signal path delay in circuit employing multiple voltage domains Grant 7,876,631 - Chai , et al. January 25, 2	2011-01-25
Self-Tuning Of Signal Path Delay In Circuit Employing Multiple Voltage Domains App 20100148839 - Chai; Chiaming ; et al.	2010-06-17

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