| Patent | Date |
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Fin Doping And Integrated Circuit Structures Resulting Therefrom
App 20220310601 - LILAK; Aaron D. ; et al. | 2022-09-29 |
Recoiled metal thin film for 3D inductor with tunable core
Grant 11,444,148 - Kim , et al. September 13, 2 | 2022-09-13 |
Backside contacts for semiconductor devices
Grant 11,437,283 - Lilak , et al. September 6, 2 | 2022-09-06 |
Metallization structures for stacked device connectivity and their methods of fabrication
Grant 11,430,814 - Lilak , et al. August 30, 2 | 2022-08-30 |
Self-aligned local interconnects
Grant 11,424,160 - Lilak , et al. August 23, 2 | 2022-08-23 |
Leave-behind Protective Layer Having Secondary Purpose
App 20220246608 - LILAK; Aaron D. ; et al. | 2022-08-04 |
Gate-all-around Integrated Circuit Structures Having Insulator Fin On Insulator Substrate
App 20220246743 - LILAK; Aaron D. ; et al. | 2022-08-04 |
Heterogeneous Ge/III-V CMOS transistor structures
Grant 11,398,479 - Rachmady , et al. July 26, 2 | 2022-07-26 |
Isolation wall stressor structures to improve channel stress and their methods of fabrication
Grant 11,393,722 - Lilak , et al. July 19, 2 | 2022-07-19 |
Stacked transistors with Si PMOS and high mobility thin film transistor NMOS
Grant 11,393,818 - Dewey , et al. July 19, 2 | 2022-07-19 |
Pedestal fin structure for stacked transistor integration
Grant 11,374,004 - Lilak , et al. June 28, 2 | 2022-06-28 |
Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor
Grant 11,374,024 - Lilak , et al. June 28, 2 | 2022-06-28 |
Leave-behind protective layer having secondary purpose
Grant 11,348,916 - Lilak , et al. May 31, 2 | 2022-05-31 |
Gate-all-around integrated circuit structures having insulator fin on insulator substrate
Grant 11,342,432 - Lilak , et al. May 24, 2 | 2022-05-24 |
Stacked Transistors
App 20220123128 - MORROW; Patrick ; et al. | 2022-04-21 |
Forksheet Transistor Architectures
App 20220102346 - LILAK; Aaron D. ; et al. | 2022-03-31 |
Vertically Stacked Transistor Devices With Isolation Wall Structures Containing An Electrical Conductor
App 20220102246 - LILAK; Aaron D. ; et al. | 2022-03-31 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20220069094 - MORROW; Patrick ; et al. | 2022-03-03 |
Methods of doping fin structures of non-planar transistor devices
Grant 11,264,453 - Weber , et al. March 1, 2 | 2022-03-01 |
Stacked transistors
Grant 11,257,929 - Morrow , et al. February 22, 2 | 2022-02-22 |
Vertically stacked transistor devices with isolation wall structures containing an electrical conductor
Grant 11,257,738 - Lilak , et al. February 22, 2 | 2022-02-22 |
Forksheet transistor architectures
Grant 11,239,236 - Lilak , et al. February 1, 2 | 2022-02-01 |
Methods of doping fin structures of non-planar transistor devices
Grant 11,222,947 - Weber , et al. January 11, 2 | 2022-01-11 |
Backside contact structures and fabrication for metal on both sides of devices
Grant 11,201,221 - Morrow , et al. December 14, 2 | 2021-12-14 |
Vertically Stacked Transistors In A Fin
App 20210351078 - Lilak; Aaron D. ; et al. | 2021-11-11 |
Metallization Structures Under A Semiconductor Device Layer
App 20210343710 - Lilak; Aaron D. ; et al. | 2021-11-04 |
Semiconductor device having stacked transistors and multiple threshold voltage control
Grant 11,152,396 - Lilak , et al. October 19, 2 | 2021-10-19 |
Gate-all-around Integrated Circuit Structures Having Insulator Fin On Insulator Substrate
App 20210305388 - LILAK; Aaron D. ; et al. | 2021-09-30 |
Forksheet Transistor Architectures
App 20210296315 - LILAK; Aaron D. ; et al. | 2021-09-23 |
Systems and methods to reduce FinFET gate capacitance
Grant 11,107,924 - Lilak , et al. August 31, 2 | 2021-08-31 |
Metallization structures under a semiconductor device layer
Grant 11,107,811 - Lilak , et al. August 31, 2 | 2021-08-31 |
Bottom fin trim isolation aligned with top gate for stacked device architectures
Grant 11,075,202 - Lilak , et al. July 27, 2 | 2021-07-27 |
Stacked transistor architecture having diverse fin geometry
Grant 11,075,198 - Lilak , et al. July 27, 2 | 2021-07-27 |
Vertically stacked transistors in a pin
Grant 11,075,119 - Lilak , et al. July 27, 2 | 2021-07-27 |
Pn-body-tied Field Effect Transistors
App 20210193802 - Lilak; Aaron D. ; et al. | 2021-06-24 |
Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability
Grant 11,011,537 - Lilak , et al. May 18, 2 | 2021-05-18 |
Vertically stacked devices with self-aligned regions formed by direct self assembly (DSA) processing
Grant 10,991,696 - Lilak , et al. April 27, 2 | 2021-04-27 |
Methods and apparatus to remove epitaxial defects in semiconductors
Grant 10,978,590 - Lilak , et al. April 13, 2 | 2021-04-13 |
Stacked Transistors With Si Pmos And High Mobility Thin Film Transistor Nmos
App 20210091080 - DEWEY; Gilbert ; et al. | 2021-03-25 |
Bottom Fin Trim Isolation Aligned With Top Gate For Stacked Device Architectures
App 20210074704 - Lilak; Aaron D. ; et al. | 2021-03-11 |
Methods and apparatus for gettering impurities in semiconductors
Grant 10,937,665 - Lilak , et al. March 2, 2 | 2021-03-02 |
Iii-v Source/drain In Top Nmos Transistors For Low Temperature Stacked Transistor Contacts
App 20210057413 - DEWEY; Gilbert ; et al. | 2021-02-25 |
Backside fin recess control with multi-HSI option
Grant 10,910,405 - Lilak , et al. February 2, 2 | 2021-02-02 |
Device isolation by fixed charge
Grant 10,892,335 - Ma , et al. January 12, 2 | 2021-01-12 |
Memory Devices With A Logic Region Between Memory Regions
App 20200411428 - Lilak; Aaron D. ; et al. | 2020-12-31 |
Vertically Stacked Memory Elements With Air Gap
App 20200403033 - Lilak; Aaron D. ; et al. | 2020-12-24 |
Metallization Structures For Stacked Device Connectivity And Their Methods Of Fabrication
App 20200395386 - Lilak; Aaron D. ; et al. | 2020-12-17 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20200381525 - MORROW; Patrick ; et al. | 2020-12-03 |
Heterogeneous Ge/iii-v Cmos Transistor Structures
App 20200312846 - Rachmady; Willy ; et al. | 2020-10-01 |
Isolation Wall Stressor Structures To Improve Channel Stress And Their Methods Of Fabrication
App 20200303257 - Lilak; Aaron D. ; et al. | 2020-09-24 |
Backside contact structures and fabrication for metal on both sides of devices
Grant 10,784,358 - Morrow , et al. Sept | 2020-09-22 |
Stacked Transistors Having Device Strata With Different Channel Widths
App 20200295003 - Dewey; Gilbert W. ; et al. | 2020-09-17 |
Backside Contacts For Semiconductor Devices
App 20200294998 - LILAK; AARON D. ; et al. | 2020-09-17 |
Stacked Transistors With Different Crystal Orientations In Different Device Strata
App 20200295127 - Mannebach; Ehren ; et al. | 2020-09-17 |
Etchstop Regions In Fins Of Semiconductor Devices
App 20200279941 - HUANG; Cheng-Ying ; et al. | 2020-09-03 |
Vertically Stacked Transistor Devices With Isolation Wall Structures Containing An Electrical Conductor
App 20200273779 - LILAK; Aaron D. ; et al. | 2020-08-27 |
Stacked Transistors With Dielectric Between Channels Of Different Device Strata
App 20200266218 - Lilak; Aaron D. ; et al. | 2020-08-20 |
Self-aligned Local Interconnects
App 20200258778 - A1 | 2020-08-13 |
Vertical Diode In Stacked Transistor Architecture
App 20200258881 - A1 | 2020-08-13 |
Semiconductor Device Having Stacked Transistors And Multiple Threshold Voltage Control
App 20200251502 - Kind Code | 2020-08-06 |
Stacked Transistor Architecture Having Diverse Fin Geometry
App 20200235092 - Lilak; Aaron D. ; et al. | 2020-07-23 |
Integrated Circuits With Stacked Transistors And Methods Of Manufacturing The Same Using Processes Which Fabricate Lower Gate St
App 20200235134 - Lilak; Aaron D. ; et al. | 2020-07-23 |
Recoiled Metal Thin Film For 3d Inductor With Tunable Core
App 20200194540 - KIM; Gwang-Soo ; et al. | 2020-06-18 |
Device Isolation By Fixed Charge
App 20200185501 - Ma; Sean T. ; et al. | 2020-06-11 |
Backside Fin Recess Control With Multi-hsi Option
App 20200176482 - LILAK; Aaron D. ; et al. | 2020-06-04 |
Metallization Structures Under A Semiconductor Device Layer
App 20200161298 - Lilak; Aaron D. ; et al. | 2020-05-21 |
Deep EPI enabled by backside reveal for stress enhancement and contact
Grant 10,636,907 - Lilak , et al. | 2020-04-28 |
Backside fin recess control with multi-hsi option
Grant 10,600,810 - Lilak , et al. | 2020-03-24 |
Structures And Methods For Memory Cells
App 20200083225 - Ma; Sean T. ; et al. | 2020-03-12 |
Backside isolation for integrated circuit
Grant 10,573,715 - Lilak , et al. Feb | 2020-02-25 |
Subfin Leakage Suppression Using Fixed Charge
App 20200044059 - Ma; Sean T. ; et al. | 2020-02-06 |
Integrated circuit with stacked transistor devices
Grant 10,546,873 - Mehandru , et al. Ja | 2020-01-28 |
Long channel MOS transistors for low leakage applications on a short channel CMOS chip
Grant 10,529,827 - Mehandru , et al. J | 2020-01-07 |
Techniques For Forming Gate Structures For Transistors Arranged In A Stacked Configuration On A Single Fin Structure
App 20200006331 - LILAK; AARON D. ; et al. | 2020-01-02 |
Pedestal Fin Structure For Stacked Transistor Integration
App 20200006340 - LILAK; AARON D. ; et al. | 2020-01-02 |
Leave-behind Protective Layer Having Secondary Purpose
App 20200006330 - LILAK; AARON D. ; et al. | 2020-01-02 |
Interconnect Techniques For Electrically Connecting Source/drain Regions Of Stacked Transistors
App 20200006329 - LILAK; AARON D. ; et al. | 2020-01-02 |
Methods for doping a sub-fin region of a semiconductor structure by backside reveal and associated devices
Grant 10,497,781 - Lilak , et al. De | 2019-12-03 |
Systems And Methods To Reduce Finfet Gate Capacitance
App 20190348535 - Lilak; Aaron D. ; et al. | 2019-11-14 |
Direct Self Assembly (dsa) Processing Of Vertically Stacked Devices With Self-aligned Regions
App 20190341384 - Lilak; Aaron D. ; et al. | 2019-11-07 |
Back Side Processing Of Integrated Circuit Structures To Form Insulation Structure Between Adjacent Transistor Structures
App 20190341297 - LILAK; AARON D. ; et al. | 2019-11-07 |
Isolation structures for an integrated circuit element and method of making same
Grant 10,468,489 - Lilak , et al. No | 2019-11-05 |
Vertically Stacked Transistors In A Pin
App 20190326175 - Lilak; Aaron D. ; et al. | 2019-10-24 |
Methods Of Doping Fin Structures Of Non-planar Transistor Devices
App 20190267448 - Weber; Cory E. ; et al. | 2019-08-29 |
Vertical Interconnect Methods For Stacked Device Architectures Using Direct Self Assembly With High Operational Parallelization
App 20190221577 - LILAK; Aaron D. ; et al. | 2019-07-18 |
Stacked Transistors With Different Gate Lengths In Different Device Strata
App 20190196830 - Lilak; Aaron D. ; et al. | 2019-06-27 |
Methods And Apparatus For Gettering Impurities In Semiconductors
App 20190189464 - Lilak; Aaron D. ; et al. | 2019-06-20 |
Methods And Apparatus To Remove Epitaxial Defects In Semiconductors
App 20190189795 - Lilak; Aaron D. ; et al. | 2019-06-20 |
Finfet Transistor With Channel Stress Induced Via Stressor Material Inserted Into Fin Plug Region Enabled By Backside Reveal
App 20190172950 - LILAK; Aaron D. ; et al. | 2019-06-06 |
Backside Fin Recess Control With Multi-hsi Option
App 20190027503 - LILAK; Aaron D. ; et al. | 2019-01-24 |
Integrated Circuit With Stacked Transistor Devices
App 20180342532 - MEHANDRU; Rishabh ; et al. | 2018-11-29 |
Backside Isolation For Integrated Circuit
App 20180331183 - LILAK; AARON D. ; et al. | 2018-11-15 |
Stacked Transistors
App 20180315838 - MORROW; Patrick ; et al. | 2018-11-01 |
Methods Of Doping Fin Structures Of Non-planar Transistor Devices
App 20180254320 - Weber; Cory E. ; et al. | 2018-09-06 |
Methods For Doping A Sub-fin Region Of A Semiconductor Structure By Backside Reveal And Associated Devices
App 20180248005 - LILAK; Aaron D. ; et al. | 2018-08-30 |
Long Channel Mos Transistors For Low Leakage Applications On A Short Channel Cmos Chip
App 20180226492 - MEHANDRU; Rishabh ; et al. | 2018-08-09 |
Isolation Structures For An Integrated Circuit Element And Method Of Making Same
App 20180226478 - LILAK; Aaron D. ; et al. | 2018-08-09 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20180219075 - MORROW; Patrick ; et al. | 2018-08-02 |
Deep Epi Enabled By Backside Reveal For Stress Enhancement & Contact
App 20180212057 - LILAK; Aaron D. ; et al. | 2018-07-26 |
Semiconductor device with isolated body portion
Grant 10,026,829 - Cappellani , et al. July 17, 2 | 2018-07-17 |
Semiconductor Device With Isolated Body Portion
App 20170162676 - CAPPELLANI; Annalisa ; et al. | 2017-06-08 |
Semiconductor device with isolated body portion
Grant 9,608,059 - Cappellani , et al. March 28, 2 | 2017-03-28 |
Semiconductor Device With Isolated Body Portion
App 20130320455 - Cappellani; Annalisa ; et al. | 2013-12-05 |
High concentration indium fluorine retrograde wells
Grant 7,129,533 - Weber , et al. October 31, 2 | 2006-10-31 |
Methods of optimization of implant conditions to minimize channeling and structures formed thereby
App 20060202267 - Ranade; Pushkar ; et al. | 2006-09-14 |
Methods of optimization of implant conditions to minimize channeling and structures formed thereby
App 20060084248 - Ranade; Pushkar ; et al. | 2006-04-20 |
High concentration indium fluorine retrograde wells
Grant 6,838,329 - Weber , et al. January 4, 2 | 2005-01-04 |
High concentration indium fluorine retrograde wells
App 20040188767 - Weber, Cory E. ; et al. | 2004-09-30 |
High concentration indium fluorine retrograde wells
App 20040192055 - Weber, Cory E. ; et al. | 2004-09-30 |
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