Libera; Giovanna Dalla

Patent Applications and Registrations

Patent applications and USPTO patent grants for Libera; Giovanna Dalla.The latest application filed is for "low resistance contact structure for a select transistor of eeprom memory cells in a no-dpcc process".

Company Profile

0.5.6

Libera; Giovanna Dalla - Monza IT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuit structure with a parasitic transistor having high threshold voltage Grant 6,642,582 - Libera , et al. November 4, 2	2003-11-04
Low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process App 20020060349 - Libera, Giovanna Dalla ; et al.	2002-05-23
Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions App 20010024861 - Patelmo, Matteo ; et al.	2001-09-27
Integrated MOS transistor with a high threshold voltage and low multiplication coefficient App 20010022380 - Patelmo, Matteo ; et al.	2001-09-20
Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions App 20010021556 - Patelmo, Matteo ; et al.	2001-09-13
Process for the manufacturing of an electrically programmable non-volatile memory device App 20010021555 - Bottini, Roberta ; et al.	2001-09-13
Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions Grant 6,281,077 - Patelmo , et al. August 28, 2	2001-08-28
Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks Grant 6,274,411 - Patelmo , et al. August 14, 2	2001-08-14
Non-volatile memory structure and corresponding manufacturing process App 20010005333 - Libera, Giovanna Dalla ; et al.	2001-06-28
Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions Grant 6,251,728 - Patelmo , et al. June 26, 2	2001-06-26
EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process Grant 6,221,717 - Cremonesi , et al. April 24, 2	2001-04-24

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