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Patent applications and USPTO patent grants for Liao; Wilson Y..The latest application filed is for "multiple multi-threaded processors having an l1 instruction cache and a shared l2 instruction cache".
Patent | Date |
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Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache Grant 8,087,024 - Lakshmanamurthy , et al. December 27, 2 | 2011-12-27 |
Thread-based engine cache partitioning Grant 7,536,692 - Lakshmanamurthy , et al. May 19, 2 | 2009-05-19 |
Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache App 20090089546 - Lakshmanamurthy; Sridhar ;   et al. | 2009-04-02 |
Processing element with next and previous neighbor registers for direct data transfer Grant 7,275,145 - Lakshmanamurthy , et al. September 25, 2 | 2007-09-25 |
Processing element with next and previous neighbor registers App 20050149691 - Lakshmanamurthy, Sridhar ;   et al. | 2005-07-07 |
Servicing engine cache requests App 20050108479 - Lakshmanamurthy, Sridhar ;   et al. | 2005-05-19 |
Dynamically caching engine instructions App 20050102474 - Lakshmanamurthy, Sridhar ;   et al. | 2005-05-12 |
Thread-based engine cache partitioning App 20050102486 - Lakshmanamurthy, Sridhar ;   et al. | 2005-05-12 |
Scalable packet buffer descriptor management in ATM to ethernet bridge gateway App 20050068956 - Liao, Wilson Y. ;   et al. | 2005-03-31 |
Executing instructions on a processor App 20050050306 - Lakshmanamurthy, Sridhar ;   et al. | 2005-03-03 |
Method and process for scheduling data packet collection App 20040252687 - Lakshmanamurthy, Sridhar ;   et al. | 2004-12-16 |
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