| Patent | Date |
|---|
Self-aligned Gate Endcap (sage) Architectures With Reduced Cap
App 20220310818 - SUNG; Seung Hoon ; et al. | 2022-09-29 |
Self-aligned gate edge architecture with alternate channel material
Grant 11,456,357 - Guha , et al. September 27, 2 | 2022-09-27 |
Contact Architecture For Capacitance Reduction And Satisfactory Contact Resistance
App 20220165855 - MEHANDRU; Rishabh ; et al. | 2022-05-26 |
Self-aligned gate endcap (SAGE) architecture having endcap plugs
Grant 11,329,138 - Subramanian , et al. May 10, 2 | 2022-05-10 |
Gate And Fin Trim Isolation For Advanced Integrated Circuit Structure Fabrication
App 20220102554 - GUTTMAN; Jeremy J. ; et al. | 2022-03-31 |
Selective Growth Self-aligned Gate Endcap (sage) Architectures Without Fin End Gap
App 20220093590 - GULER; Leonard P. ; et al. | 2022-03-24 |
Contact architecture for capacitance reduction and satisfactory contact resistance
Grant 11,282,930 - Mehandru , et al. March 22, 2 | 2022-03-22 |
Dual Self-aligned Gate Endcap (sage) Architectures
App 20220077302 - SUBRAMANIAN; Sairam ; et al. | 2022-03-10 |
Field Effect Transistor With A Hybrid Gate Spacer Including A Low-k Dielectric Material
App 20220077311 - Liao; Szuya S. ; et al. | 2022-03-10 |
Unidirectional Self-aligned Gate Endcap (sage) Architectures With Gate-orthogonal Walls
App 20220077145 - HAFEZ; Walid M. ; et al. | 2022-03-10 |
Methods of doping fin structures of non-planar transistor devices
Grant 11,264,453 - Weber , et al. March 1, 2 | 2022-03-01 |
Methods of doping fin structures of non-planar transistor devices
Grant 11,222,947 - Weber , et al. January 11, 2 | 2022-01-11 |
Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls
Grant 11,217,582 - Hafez , et al. January 4, 2 | 2022-01-04 |
Source Or Drain Structures With High Surface Germanium Concentration
App 20210408275 - BOMBERGER; Cory ; et al. | 2021-12-30 |
Source Or Drain Structures With High Germanium Concentration Capping Layer
App 20210407851 - BOMBERGER; Cory ; et al. | 2021-12-30 |
Field Effect Transistor Having A Gate Dielectric With A Dipole Layer And Having A Gate Stressor Layer
App 20210408282 - TIWARI; Vishal ; et al. | 2021-12-30 |
Dual self-aligned gate endcap (SAGE) architectures
Grant 11,205,708 - Subramanian , et al. December 21, 2 | 2021-12-21 |
Field effect transistor with a hybrid gate spacer including a low-k dielectric material
Grant 11,183,592 - Liao , et al. November 23, 2 | 2021-11-23 |
Confined Epitaxial Regions For Semiconductor Devices And Methods Of Fabricating Semiconductor Devices Having Confined Epitaxial Regions
App 20210359110 - LIAO; Szuya S. ; et al. | 2021-11-18 |
Semiconductor layer between source/drain regions and gate spacers
Grant 11,152,461 - Mehandru , et al. October 19, 2 | 2021-10-19 |
Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions
Grant 11,127,841 - Liao , et al. September 21, 2 | 2021-09-21 |
Transistors employing non-selective deposition of source/drain material
Grant 11,101,268 - Jambunathan , et al. August 24, 2 | 2021-08-24 |
Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device
Grant 11,094,831 - Mehandru , et al. August 17, 2 | 2021-08-17 |
Self-aligned Gate Edge Trigate And Finfet Devices
App 20210249411 - LIAO; Szuya S. ; et al. | 2021-08-12 |
Dense memory arrays utilizing access transistors with back-side contacts
Grant 11,056,492 - Gomes , et al. July 6, 2 | 2021-07-06 |
Dense Memory Arrays Utilizing Access Transistors With Back-side Contacts
App 20210193666 - Gomes; Wilfred ; et al. | 2021-06-24 |
Self-aligned gate edge trigate and finFET devices
Grant 11,043,492 - Liao , et al. June 22, 2 | 2021-06-22 |
Integrated Circuit Device Structures And Double-sided Electrical Testing
App 20210175124 - RAO; Valluri R. ; et al. | 2021-06-10 |
Fin Shaping And Integrated Circuit Structures Resulting Therefrom
App 20210167209 - LIAO; Szuya S. ; et al. | 2021-06-03 |
Techniques for increasing channel region tensile strain in n-MOS devices
Grant 11,011,620 - Mehandru , et al. May 18, 2 | 2021-05-18 |
Selective Gate Spacers For Semiconductor Devices
App 20210143265 - Clendenning; Scott B. ; et al. | 2021-05-13 |
Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping
Grant 10,998,423 - Le , et al. May 4, 2 | 2021-05-04 |
Selective gate spacers for semiconductor devices
Grant 10,971,600 - Clendenning , et al. April 6, 2 | 2021-04-06 |
Self-aligned Gate Endcap (sage) Architectures Without Fin End Gap
App 20210091075 - LIAO; Szuya S. ; et al. | 2021-03-25 |
Contact Architecture For Capacitance Reduction And Satisfactory Contact Resistance
App 20210050423 - MEHANDRU; Rishabh ; et al. | 2021-02-18 |
Semiconductor device contacts with increased contact area
Grant 10,896,963 - Mehandru , et al. January 19, 2 | 2021-01-19 |
Contact architecture for capacitance reduction and satisfactory contact resistance
Grant 10,872,960 - Mehandru , et al. December 22, 2 | 2020-12-22 |
Self-aligned Gate Edge And Local Interconnect
App 20200388675 - WEBB; Milton Clair ; et al. | 2020-12-10 |
Self-aligned gate edge and local interconnect
Grant 10,790,354 - Webb , et al. September 29, 2 | 2020-09-29 |
Fabrication Of Multi-channel Nanowire Devices With Self-aligned Internal Spacers And Soi Finfets Using Selective Silicon Nitride
App 20200287022 - LE; Van H. ; et al. | 2020-09-10 |
Nanowire transistor device architectures
Grant 10,770,458 - Mehandru , et al. Sep | 2020-09-08 |
Selective deposition utilizing sacrificial blocking layers for semiconductor devices
Grant 10,756,215 - Kloster , et al. A | 2020-08-25 |
Fabrication of multi-channel nanowire devices with self-aligned internal spacers and SOI FinFETs using selective silicon nitride capping
Grant 10,720,508 - Le , et al. | 2020-07-21 |
Mid-processing Removal Of Semiconductor Fins During Fabrication Of Integrated Circuit Structures
App 20200227267 - Baykan; Mehmet O. ; et al. | 2020-07-16 |
Metal To Source/drain Contact Area Using Thin Nucleation Layer And Sacrificial Epitaxial Film
App 20200161440 - Jhaveri; Ritesh ; et al. | 2020-05-21 |
Contact Architecture For Capacitance Reduction And Satisfactory Contact Resistance
App 20200066851 - MEHANDRU; Rishabh ; et al. | 2020-02-27 |
Confined Epitaxial Regions For Semiconductor Devices And Methods Of Fabricating Semiconductor Devices Having Confined Epitaxial Regions
App 20200035813 - LIAO; Szuya S. ; et al. | 2020-01-30 |
Selective Gate Spacers For Semiconductor Devices
App 20200020786 - Clendenning; Scott B. ; et al. | 2020-01-16 |
Semiconductor Nanowire Device Having Cavity Spacer And Method Of Fabricating Cavity Spacer For Semiconductor Nanowire Device
App 20200013905 - MEHANDRU; Rishabh ; et al. | 2020-01-09 |
Self-aligned Gate Edge Architecture With Alternate Channel Material
App 20200006487 - Guha; Biswajeet ; et al. | 2020-01-02 |
Transistors Employing Non-selective Deposition Of Source/drain Material
App 20190355721 - JAMBUNATHAN; KARTHIK ; et al. | 2019-11-21 |
Semiconductor Layer Between Source/drain Regions And Gate Spacers
App 20190355811 - Mehandru; Rishabh ; et al. | 2019-11-21 |
Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions
Grant 10,461,177 - Liao , et al. Oc | 2019-10-29 |
Self-aligned Gate Edge And Local Interconnect And Method To Fabricate Same
App 20190326391 - WEBB; Milton Clair ; et al. | 2019-10-24 |
Semiconductor nanowire device having cavity spacer and method of fabricating cavity spacer for semiconductor nanowire device
Grant 10,453,967 - Mehandru , et al. Oc | 2019-10-22 |
Unidirectional Self-aligned Gate Endcap (sage) Architectures With Gate-orthogonal Walls
App 20190304971 - HAFEZ; Walid M. ; et al. | 2019-10-03 |
Dual Self-aligned Gate Endcap (sage) Architectures
App 20190305112 - SUBRAMANIAN; Sairam ; et al. | 2019-10-03 |
Self-aligned Gate Endcap (sage) Architecture Having Endcap Plugs
App 20190305111 - SUBRAMANIAN; Sairam ; et al. | 2019-10-03 |
Nanowire Transistor Device Architectures
App 20190279978 - MEHANDRU; RISHABH ; et al. | 2019-09-12 |
Confined and scalable helmet
Grant 10,410,867 - Sharma , et al. Sept | 2019-09-10 |
Methods Of Doping Fin Structures Of Non-planar Transistor Devices
App 20190267448 - Weber; Cory E. ; et al. | 2019-08-29 |
Selective gate spacers for semiconductor devices
Grant 10,396,176 - Clendenning , et al. A | 2019-08-27 |
Techniques For Increasing Channel Region Tensile Strain In N-mos Devices
App 20190207015 - MEHANDRU; RISHABH ; et al. | 2019-07-04 |
Selective Deposition Utilizing Sacrificial Blocking Layers For Semiconductor Devices
App 20190189803 - KLOSTER; Grant ; et al. | 2019-06-20 |
Self-aligned gate edge and local interconnect and method to fabricate same
Grant 10,319,812 - Webb , et al. | 2019-06-11 |
Self-aligned Gate Edge Trigate And Finfet Devices
App 20190139957 - LIAO; Szuya S. ; et al. | 2019-05-09 |
Selective deposition utilizing sacrificial blocking layers for semiconductor devices
Grant 10,243,080 - Kloster , et al. | 2019-03-26 |
Confined And Scalable Helmet
App 20180315607 - Sharma; Vyom ; et al. | 2018-11-01 |
Methods Of Doping Fin Structures Of Non-planar Transistor Devices
App 20180254320 - Weber; Cory E. ; et al. | 2018-09-06 |
Semiconductor Device Contacts With Increased Contact Area
App 20180248011 - MEHANDRU; RISHABH ; et al. | 2018-08-30 |
Resistance Reduction Under Transistor Spacers
App 20180240874 - WEBER; CORY E. ; et al. | 2018-08-23 |
Fabrication Of Multi-channel Nanowire Devices With Self-aligned Internal Spacers And Soi Finfets Using Selective Silicon Nitride Capping
App 20180226490 - LE; Van H. ; et al. | 2018-08-09 |
Selective Gate Spacers For Semiconductor Devices
App 20180219080 - CLENDENNING; Scott B. ; et al. | 2018-08-02 |
Semiconductor Nanowire Device Having Cavity Spacer And Method Of Fabricating Cavity Spacer For Semiconductor Nanowire Device
App 20180204955 - MEHANDRU; Rishabh ; et al. | 2018-07-19 |
Confined Epitaxial Regions for Semiconductor Devices and Methods of Fabricating Semiconductor Devices Having Confined Epitaxial Regions
App 20180158930 - LIAO; Szuya S. ; et al. | 2018-06-07 |
Self-aligned Gate Edge And Local Interconnect And Method To Fabricate Same
App 20180047808 - WEBB; Milton Clair ; et al. | 2018-02-15 |
Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions
Grant 9,882,027 - Liao , et al. January 30, 2 | 2018-01-30 |
Self-aligned gate edge and local interconnect and method to fabricate same
Grant 9,831,306 - Webb , et al. November 28, 2 | 2017-11-28 |
Selective Deposition Utilizing Sacrificial Blocking Layers For Semiconductor Devices
App 20170330972 - KLOSTER; GRANT ; et al. | 2017-11-16 |
Confined Epitaxial Regions for Semiconductor Devices and Methods of Fabricating Semiconductor Devices Having Confined Epitaxial Regions
App 20170054003 - LIAO; Szuya S. ; et al. | 2017-02-23 |
Self-Aligned Gate Edge and Local Interconnect and Method to Fabricate Same
App 20160233298 - WEBB; Milton C. ; et al. | 2016-08-11 |
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