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Patent applications and USPTO patent grants for Liao; Hsien-Huang.The latest application filed is for "integrated circuit layouts with line-end extensions".
Patent | Date |
---|---|
Semiconductor device and method Grant 11,393,724 - Wu , et al. July 19, 2 | 2022-07-19 |
Integrated Circuit Layouts with Line-End Extensions App 20210192121 - Liao; Hsien-Huang ;   et al. | 2021-06-24 |
Semiconductor Device and Method App 20210166977 - Wu; Shih-Chieh ;   et al. | 2021-06-03 |
Semiconductor device and method Grant 10,957,604 - Wu , et al. March 23, 2 | 2021-03-23 |
Integrated circuit layouts with line-end extensions Grant 10,943,054 - Liao , et al. March 9, 2 | 2021-03-09 |
Integrated circuit layouts with line-end extensions Grant 10,803,227 - Liao , et al. October 13, 2 | 2020-10-13 |
Semiconductor Device and Method App 20200135579 - Wu; Shih-Chieh ;   et al. | 2020-04-30 |
Integrated Circuit Layouts with Line-End Extensions App 20200082055 - Liao; Hsien-Huang ;   et al. | 2020-03-12 |
Integrated Circuit Layouts with Line-End Extensions App 20190065654 - Liao; Hsien-Huang ;   et al. | 2019-02-28 |
Method and apparatus for reducing implant topography reflection effect Grant 8,572,519 - Liu , et al. October 29, 2 | 2013-10-29 |
Method And Apparatus For Reducing Implant Topography Reflection Effect App 20110252387 - Liu; Wen Hao ;   et al. | 2011-10-13 |
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