LIAO; Chin-Chang

Patent Applications and Registrations

Patent applications and USPTO patent grants for LIAO; Chin-Chang.The latest application filed is for "conductive bump electrode structure".

Company Profile

1.10.11

LIAO; Chin-Chang - Zhubei City TW
Liao; Chin-Chang - Hsinchu County TW
Liao; Chin Chang - Shanghai CN
Liao; Chin-Chang - Taipei City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Conductive Bump Electrode Structure App 20210368619 - LIAO; Chin-Chang ; et al.	2021-11-25
System and method for measuring physiological signal Grant 10,980,464 - Liao April 20, 2	2021-04-20
Physiological signal receiving apparatus and manufacturing method thereof Grant 10,524,678 - Liao , et al. J	2020-01-07
System And Method For Measuring Physiological Signal App 20190046060 - Liao; Chin-Chang	2019-02-14
Physiological Signal Receiving Apparatus And Manufacturing Method Thereof App 20180263525 - Liao; Chin-Chang ; et al.	2018-09-20
System and method for test structure on a wafer Grant 9,472,476 - Ping , et al. October 18, 2	2016-10-18
System and method for I/O ESD protection with floating and/or biased polysilicon regions Grant 8,686,507 - Su , et al. April 1, 2	2014-04-01
System And Method For Test Structure On A Wafer App 20130193997 - Ping; Wang Jian ; et al.	2013-08-01
Electronic Device App 20130164588 - Liao; Chin-Chang ; et al.	2013-06-27
System and method for test structure on a wafer Grant 8,415,663 - Ping , et al. April 9, 2	2013-04-09
System and method for input pin ESD protection with floating and/or biased polysilicon regions Grant 8,319,286 - Su , et al. November 27, 2	2012-11-27
System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors Grant 8,283,726 - Su , et al. October 9, 2	2012-10-09
System And Method For Input Pin Esd Protection With Floating And/or Biased Polysilicon Regions App 20120001261 - Su; Ting Chieh ; et al.	2012-01-05
System And Method For Test Structure On A Wafer App 20100164508 - PING; WANG JIAN ; et al.	2010-07-01
System And Method For I/o Esd Protection With Polysilicon Regions Fabricated By Processes For Making Core Transistors App 20100059824 - SU; TING CHIEH ; et al.	2010-03-11
System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors Grant 7,642,602 - Su , et al. January 5, 2	2010-01-05
System And Method For I/o Esd Protection With Polysilicon Regions Fabricated By Processes For Making Core Transistors App 20070284663 - Su; Ting Chieh ; et al.	2007-12-13
System and method for I/O ESD protection with floating and/or biased polysilicon regions App 20070164362 - Su; Ting Chieh ; et al.	2007-07-19

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