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Pillar-shaped Semiconductor Device And Manufacturing Method Thereof
App 20220028869 - MASUOKA; Fujio ; et al. | 2022-01-27 |
Method For Manufacturing Three-Dimensional Semiconductor Device
App 20210358754 - MASUOKA; Fujio ; et al. | 2021-11-18 |
Semiconductor device production method and semiconductor device
Grant 9,666,688 - Masuoka , et al. May 30, 2 | 2017-05-30 |
Semiconductor Device Production Method And Semiconductor Device
App 20160380080 - MASUOKA; Fujio ; et al. | 2016-12-29 |
Semiconductor device production method and semiconductor device
Grant 9,490,362 - Masuoka , et al. November 8, 2 | 2016-11-08 |
Semiconductor Device And Production Method
App 20160308013 - MASUOKA; Fujio ; et al. | 2016-10-20 |
Integrated circuit system with double doped drain transistor
Grant 9,269,770 - Li , et al. February 23, 2 | 2016-02-23 |
Surrounding Gate Transistor (sgt) Structure
App 20150357428 - MASUOKA; Fujio ; et al. | 2015-12-10 |
Semiconductor Device Production Method And Semiconductor Device
App 20150287822 - MASUOKA; Fujio ; et al. | 2015-10-08 |
Surrounding gate transistor (SGT) structure
Grant 9,153,697 - Masuoka , et al. October 6, 2 | 2015-10-06 |
Surround gate CMOS semiconductor device
Grant 8,609,494 - Masuoka , et al. December 17, 2 | 2013-12-17 |
Surround Gate Cmos Semiconductor Device
App 20130252413 - MASUOKA; Fujio ; et al. | 2013-09-26 |
Surround gate CMOS semiconductor device
Grant 8,486,785 - Masuoka , et al. July 16, 2 | 2013-07-16 |
Semiconductor structure including high voltage device
Grant 8,410,553 - Koo , et al. April 2, 2 | 2013-04-02 |
LDMOS using a combination of enhanced dielectric stress layer and dummy gates
Grant 8,334,567 - Chu , et al. December 18, 2 | 2012-12-18 |
High performance LDMOS device having enhanced dielectric strain layer
Grant 8,293,614 - Chu , et al. October 23, 2 | 2012-10-23 |
High Performance Ldmos Device Having Enhanced Dielectric Strain Layer
App 20120119293 - Chu; Sanford ; et al. | 2012-05-17 |
High performance LDMOS device having enhanced dielectric strain layer
Grant 8,163,621 - Chu , et al. April 24, 2 | 2012-04-24 |
Semiconductor Device And Production Method
App 20110303973 - Masuoka; Fujio ; et al. | 2011-12-15 |
Semiconductor Device And Fabrication Method Therefor
App 20110303985 - Masuoka; Fujio ; et al. | 2011-12-15 |
Integrated circuit system employing an elevated drain
Grant 7,951,680 - Zhang , et al. May 31, 2 | 2011-05-31 |
Semiconductor Structure Including High Voltage Device
App 20110079850 - KOO; Jeoung Mo ; et al. | 2011-04-07 |
LDMOS Using A Combination of Enhanced Dielectric Stress Layer and Dummy Gates
App 20110042743 - CHU; Sanford ; et al. | 2011-02-24 |
Structure and method to form source and drain regions over doped depletion regions
Grant 7,888,752 - Chui , et al. February 15, 2 | 2011-02-15 |
Semiconductor structure including high voltage device
Grant 7,867,862 - Koo , et al. January 11, 2 | 2011-01-11 |
LDMOS using a combination of enhanced dielectric stress layer and dummy gates
Grant 7,824,968 - Chu , et al. November 2, 2 | 2010-11-02 |
Integrated Circuit System Employing An Elevated Drain
App 20100109097 - Zhang; Guowei ; et al. | 2010-05-06 |
Integrated Circuit System Employing Stress-engineered Layers
App 20100109045 - Liu; Jin Ping ; et al. | 2010-05-06 |
High Performance Ldmos Device Having Enhanced Dielectric Strain Layer
App 20090302385 - Chu; Sanford ; et al. | 2009-12-10 |
Semiconductor device layout and channeling implant process
Grant 7,573,099 - Li , et al. August 11, 2 | 2009-08-11 |
Semiconductor Structure Including High Voltage Device
App 20090072310 - KOO; Jeoung Mo ; et al. | 2009-03-19 |
LDMOS using a combination of enhanced dielectric stress layer and dummy gates
App 20080014690 - Chu; Sanford ; et al. | 2008-01-17 |
Integrated Circuit System With Double Doped Drain Transistor
App 20070210376 - Li; Yisuo ; et al. | 2007-09-13 |
Shallow low energy ion implantation into pad oxide for improving threshold voltage stability
Grant 7,259,072 - Li , et al. August 21, 2 | 2007-08-21 |
Semiconductor device layout and channeling implant process
Grant 7,253,483 - Li , et al. August 7, 2 | 2007-08-07 |
Structure and method to form source and drain regions over doped depletion regions
App 20070178652 - Chui; King Jien ; et al. | 2007-08-02 |
Structure and method to form source and drain regions over doped depletion regions
Grant 7,202,133 - Chui , et al. April 10, 2 | 2007-04-10 |
Low cost source drain elevation through poly amorphizing implant technology
Grant 7,101,743 - Li , et al. September 5, 2 | 2006-09-05 |
Semiconductor device layout and channeling implant process
App 20050280082 - Li, Yisuo ; et al. | 2005-12-22 |
Semiconductor device layout and channeling implant process
Grant 6,972,236 - Li , et al. December 6, 2 | 2005-12-06 |
Semiconductor device layout and channeling implant process
App 20050236677 - Li, Yisuo ; et al. | 2005-10-27 |
Shallow low energy ion implantation into pad oxide for improving threshold voltage stability
App 20050239256 - Li, Yisuo ; et al. | 2005-10-27 |
Semiconductor Device Layout And Channeling Implant Process
App 20050170595 - Li, Yisuo ; et al. | 2005-08-04 |
Structure and method to form source and drain regions over doped depletion regions
App 20050156253 - Chui, King Jien ; et al. | 2005-07-21 |
Low Cost Source Drain Elevation Through Poly Amorphizing Implant Technology
App 20050148125 - Li, Yisuo ; et al. | 2005-07-07 |
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