loadpatents
name:-0.013200044631958
name:-0.020795106887817
name:-0.00037598609924316
Li; Li-Chun Patent Filings

Li; Li-Chun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Li; Li-Chun.The latest application filed is for "chip package structure and method for manufacturing chip package structure".

Company Profile
0.16.13
  • Li; Li-Chun - Hsinchu TW
  • Li; Li Chun - Shenzhen CN
  • Li; Li-Chun - Los Gatos CA
  • Li; Li-Chun - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Chip Package Structure And Method For Manufacturing Chip Package Structure
App 20150347806 - Li; Li-Chun ;   et al.
2015-12-03
Online Trading Of Virtual Characters
App 20140162765 - Bai; Jie ;   et al.
2014-06-12
Nonvolatile memories with asymmetric transistors, nonvolatile memories with high voltage lines extending in the column direction, and nonvolatile memories with decoding circuits sharing a common area
Grant 7,046,551 - Park , et al. May 16, 2
2006-05-16
Writing data to nonvolatile memory
Grant 6,987,695 - Park , et al. January 17, 2
2006-01-17
Electronic memory, such as flash EPROM, with bitwise-adjusted writing current or/and voltage
Grant 6,975,535 - Kim , et al. December 13, 2
2005-12-13
Electronic memory, such as flash EPROM, with bitwise-adjusted writing current or/and voltage
App 20050036346 - Kim, Youngweon ;   et al.
2005-02-17
Method for fabricating an integrated circuit with a transistor electrode
App 20040224452 - Li, Li-Chun ;   et al.
2004-11-11
Nonvolatile memories with asymmetric transistors, nonvolatile memories with high voltage lines extending in the column direction, and nonvolatile memories with decoding circuits sharing a common area
App 20040190343 - Park, Jongmin ;   et al.
2004-09-30
Writing data to nonvolatile memory
App 20040190344 - Park, Jongmin ;   et al.
2004-09-30
Method for fabricating an integrated circuit with a transistor electrode
Grant 6,777,280 - Li , et al. August 17, 2
2004-08-17
Nonvolatile memory structures and fabrication methods
Grant 6,757,199 - Tuan , et al. June 29, 2
2004-06-29
Memory refresh methods and circuits
Grant 6,721,224 - Eaton , et al. April 13, 2
2004-04-13
Memory Refresh Methods And Circuits
App 20040037142 - Eaton, Steve S. ;   et al.
2004-02-26
Nonvolatile memory structures and access methods
Grant 6,674,669 - Tuan , et al. January 6, 2
2004-01-06
Nonvolatile memory structures and fabrication methods
App 20030206447 - Tuan, Hsing Ti ;   et al.
2003-11-06
Nonvolatile memory structures and fabrication methods
Grant 6,643,186 - Tuan , et al. November 4, 2
2003-11-04
Nonvolatile memory structures and fabrication methods
Grant 6,617,636 - Tuan , et al. September 9, 2
2003-09-09
Nonvolatile Memory structures and access methods
App 20030067806 - Tuan, Hsing T. ;   et al.
2003-04-10
Nonvolatile memory structures and access methods
App 20030067808 - Tuan, Hsing T. ;   et al.
2003-04-10
Method For Fabricating an Integrated Circuit with a Transistor Electrode
App 20020123184 - Li, Li-Chun ;   et al.
2002-09-05
Nonvolatile memory structures and fabrication methods
App 20020042180 - Tuan, Hsing Ti ;   et al.
2002-04-11
Nonvolatile memory structures and fabrication methods
App 20020038897 - Tuan, Hsing Ti ;   et al.
2002-04-04
Memory burst operations in which address count bits are used as column address bits for one, but not both, of the odd and even columns selected in parallel.
Grant 6,191,997 - Son , et al. February 20, 2
2001-02-20
Biasing an integrated circuit well with a transistor electrode
Grant 6,133,597 - Li , et al. October 17, 2
2000-10-17
I/O bias circuit insensitive to inadvertent power supply variations for MOS memory
Grant 5,949,722 - Liu , et al. September 7, 1
1999-09-07
Using the internal supply voltage ramp rate to prevent premature enabling of a device during power-up
Grant 5,912,571 - Li , et al. June 15, 1
1999-06-15
Simulated DRAM memory bit line/bit line for circuit timing and voltage level tracking
Grant 5,828,609 - Li , et al. October 27, 1
1998-10-27
DRAM with edge sense amplifiers which are activated along with sense amplifiers internal to the array during a read cycle
Grant 5,757,710 - Li , et al. May 26, 1
1998-05-26
Integrated circuit memory with decoded address sustain circuitry for multiplexed address architecture and method
Grant 5,245,583 - Li , et al. September 14, 1
1993-09-14

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