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Patent applications and USPTO patent grants for Li; Jeong-Tyng.The latest application filed is for "extensible layer mapping for in-design verification".
Patent | Date |
---|---|
Extensible layer mapping for in-design verification Grant 11,144,690 - Wang , et al. October 12, 2 | 2021-10-12 |
Extensible Layer Mapping For In-design Verification App 20200202061 - Wang; Jun ;   et al. | 2020-06-25 |
Timing of a circuit design Grant 7,917,881 - Chen , et al. March 29, 2 | 2011-03-29 |
Optimizing a circuit design Grant 7,739,630 - Chen , et al. June 15, 2 | 2010-06-15 |
Structure and method for providing reconfigurable emulation circuit Grant 5,835,751 - Chen , et al. November 10, 1 | 1998-11-10 |
Methods for controlling timing in a logic emulation system Grant 5,649,167 - Chen , et al. July 15, 1 | 1997-07-15 |
Structure and method for providing a reconfigurable emulation circuit without hold time violations Grant 5,475,830 - Chen , et al. December 12, 1 | 1995-12-12 |
Method and apparatus for debugging reconfigurable emulation systems Grant 5,425,036 - Liu , et al. June 13, 1 | 1995-06-13 |
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