loadpatents
name:-0.010931968688965
name:-0.0076639652252197
name:-0.0048089027404785
Li; Chien-Mo Patent Filings

Li; Chien-Mo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Li; Chien-Mo.The latest application filed is for "asynchronous circuits and test methods".

Company Profile
3.7.8
  • Li; Chien-Mo - Hsinchu TW
  • Li; Chien-Mo - New Taipei TW
  • Li; Chien-Mo - New Taipei City TW
  • Li; Chien-Mo - Taipei TW
  • Li; Chien-Mo - Taipei City TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Asynchronous Circuits And Test Methods
App 20210325458 - Shen; Ting-Yu ;   et al.
2021-10-21
Design-for-test for asynchronous circuit elements
Grant 11,073,552 - Huang , et al. July 27, 2
2021-07-27
Asynchronous circuits and test methods
Grant 11,047,911 - Shen , et al. June 29, 2
2021-06-29
Asynchronous Circuits And Test Methods
App 20200132759 - Shen; Ting-Yu ;   et al.
2020-04-30
Design-For-Test for Asynchronous Circuit Elements
App 20200025826 - Huang; Kuan-Yen ;   et al.
2020-01-23
Design-for-test for asynchronous circuit elements
Grant 10,429,440 - Huang , et al. October 1, 2
2019-10-01
Design-For-Test for Asynchronous Circuit Elements
App 20190033366 - Huang; Kuan-Yen ;   et al.
2019-01-31
Multiple defect diagnosis method and machine readable media
Grant 9,983,264 - Hsueh , et al. May 29, 2
2018-05-29
Systematic defect analysis method and machine readable media
Grant 9,213,799 - Hsueh , et al. December 15, 2
2015-12-15
Multiple Defect Diagnosis Method And Machine Readable Media
App 20150204939 - Hsueh; Pei-Ying ;   et al.
2015-07-23
Systematic Defect Analysis Method And Machine Readable Media
App 20150205907 - Hsueh; Pei-Ying ;   et al.
2015-07-23
Method for creating test clock domain during integrated circuit design, and associated computer readable medium
Grant 8,468,407 - Chang , et al. June 18, 2
2013-06-18
Method For Creating Test Clock Domain During Integrated Circuit Design, And Associated Computer Readable Medium
App 20120233513 - Chang; Ming-Tung ;   et al.
2012-09-13
Asynchronous Scan Chain Circuit
App 20100185909 - Li; Chien-Mo ;   et al.
2010-07-22

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