| Patent | Date |
|---|
Data processing system with backplane and processor books configurable to support both technical and commercial workloads
Grant 7,526,631 - Arimilli , et al. April 28, 2 | 2009-04-28 |
Method And Apparatus For Modifying Existing Circuit Design
App 20080270955 - Isakson; John Mack ; et al. | 2008-10-30 |
Data Processing System With Backplane And Processor Books Configurable To Suppprt Both Technical And Commercial Workloads
App 20080209163 - Arimilli; Ravi Kumar ; et al. | 2008-08-28 |
Multiprocessor data processing system having scalable data interconnect and data routing mechanism
Grant 7,308,558 - Arimilli , et al. December 11, 2 | 2007-12-11 |
Method and apparatus for performing bus tracing with scalable bandwidth in a data processing system having a distributed memory
Grant 7,302,616 - Dodson , et al. November 27, 2 | 2007-11-27 |
Method and apparatus for performing imprecise bus tracing in a data processing system having a distributed memory
Grant 7,213,169 - Dodson , et al. May 1, 2 | 2007-05-01 |
Multiprocessor data processing system having a data routing mechanism regulated through control communication
Grant 7,007,128 - Arimilli , et al. February 28, 2 | 2006-02-28 |
Multiprocessor data processing system having a data routing mechanism regulated through control communication
App 20050149660 - Arimilli, Ravi Kumar ; et al. | 2005-07-07 |
Multiprocessor data processing system having scalable data interconnect and data routing mechanism
App 20050149692 - Arimilli, Ravi Kumar ; et al. | 2005-07-07 |
Method and apparatus for transmitting packets within a symmetric multiprocessor system
Grant 6,910,062 - Arimilli , et al. June 21, 2 | 2005-06-21 |
Robust system bus recovery
Grant 6,865,695 - Joyner , et al. March 8, 2 | 2005-03-08 |
Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response
Grant 6,848,003 - Arimilli , et al. January 25, 2 | 2005-01-25 |
Processor book for building large scalable processor systems
App 20040236891 - Arimilli, Ravi Kumar ; et al. | 2004-11-25 |
Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem
Grant 6,823,471 - Arimilli , et al. November 23, 2 | 2004-11-23 |
Data processing system having novel interconnect for supporting both technical and commercial workloads
App 20040215926 - Arimilli, Ravi Kumar ; et al. | 2004-10-28 |
Method and apparatus for performing imprecise bus tracing in a data processing system having a distributed memory
App 20040199823 - Dodson, John Steven ; et al. | 2004-10-07 |
Method and apparatus for performing bus tracing with scalable bandwidth in a data processing system having a distributed memory
App 20040199902 - Dodson, John Steven ; et al. | 2004-10-07 |
Method and apparatus for performing bus tracing in a data processing system having a distributed memory
App 20040199722 - Dodson, John Steven ; et al. | 2004-10-07 |
Imprecise snooping based invalidation mechanism
Grant 6,801,984 - Arimilli , et al. October 5, 2 | 2004-10-05 |
Cache coherency protocol with tagged intervention of modified values
Grant 6,701,416 - Arimilli , et al. March 2, 2 | 2004-03-02 |
Multi-node data processing system having a non-hierarchical interconnect architecture
Grant 6,671,712 - Arimilli , et al. December 30, 2 | 2003-12-30 |
Fixed bus tags for SMP buses
Grant 6,662,216 - Arimilli , et al. December 9, 2 | 2003-12-09 |
Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction
Grant 6,658,556 - Arimilli , et al. December 2, 2 | 2003-12-02 |
Cache-coherency protocol with recently read state for extending cache horizontally
Grant 6,658,536 - Arimilli , et al. December 2, 2 | 2003-12-02 |
Data processing system with HSA (hashed storage architecture)
Grant 6,598,118 - Arimilli , et al. July 22, 2 | 2003-07-22 |
Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response
Grant 6,591,307 - Arimilli , et al. July 8, 2 | 2003-07-08 |
Multiprocessor system bus protocol with group addresses, responses, and priorities
Grant 6,591,321 - Arimilli , et al. July 8, 2 | 2003-07-08 |
Scarfing within a hierarchical memory architecture
Grant 6,587,924 - Arimilli , et al. July 1, 2 | 2003-07-01 |
Elimination of vertical bus queueing within a hierarchical memory architecture
Grant 6,587,925 - Arimilli , et al. July 1, 2 | 2003-07-01 |
Bus master for SMP execution of global operations utilizing a single token with implied release
Grant 6,553,442 - Arimilli , et al. April 22, 2 | 2003-04-22 |
Robust system bus recovery
App 20030033555 - Joyner, Jody Bern ; et al. | 2003-02-13 |
Method and apparatus for transmitting packets within a symmetric multiprocessor system
App 20030033350 - Arimilli, Ravi Kumar ; et al. | 2003-02-13 |
Multi-node data processing system and communication protocol having a partial combined response
Grant 6,519,649 - Arimilli , et al. February 11, 2 | 2003-02-11 |
Elimination of vertical bus queueing within a hierarchical memory architecture
App 20030014592 - Arimilli, Ravi Kumar ; et al. | 2003-01-16 |
Scarfing within a hierarchical memory architecture
App 20030014591 - Arimilli, Ravi Kumar ; et al. | 2003-01-16 |
Incremental tag build for hierarchical memory architecture
App 20030014593 - Arimilli, Ravi Kumar ; et al. | 2003-01-16 |
Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens
Grant 6,507,880 - Arimilli , et al. January 14, 2 | 2003-01-14 |
Method for just-in-time delivery of load data by intervening caches
Grant 6,505,277 - Arimilli , et al. January 7, 2 | 2003-01-07 |
Imprecise snooping based invalidation mechanism
App 20030005236 - Arimilli, Ravi Kumar ; et al. | 2003-01-02 |
Cache having virtual cache controller queues
Grant 6,502,168 - Arimilli , et al. December 31, 2 | 2002-12-31 |
Bus protocol and token manager for SMP execution of global operations utilizing a single token with implied release
Grant 6,480,915 - Arimilli , et al. November 12, 2 | 2002-11-12 |
ECC mechanism for set associative cache array
Grant 6,480,975 - Arimilli , et al. November 12, 2 | 2002-11-12 |
Cache index based system address bus
Grant 6,477,613 - Arimilli , et al. November 5, 2 | 2002-11-05 |
Processor assigning data to hardware partition based on selectable hash of data address
Grant 6,470,442 - Arimilli , et al. October 22, 2 | 2002-10-22 |
Removal of posted operations from cache operations queue
Grant 6,418,514 - Arimilli , et al. July 9, 2 | 2002-07-09 |
Multiprocessor system with a high performance integrated distributed switch (IDS) controller
Grant 6,415,424 - Arimilli , et al. July 2, 2 | 2002-07-02 |
Cache-coherency protocol with upstream undefined state
Grant 6,374,330 - Arimilli , et al. April 16, 2 | 2002-04-16 |
Method and system for communication in which a castout operation is cancelled in response to snoop responses
Grant 6,349,367 - Arimilli , et al. February 19, 2 | 2002-02-19 |
Cache coherency protocols with posted operations
Grant 6,347,361 - Arimilli , et al. February 12, 2 | 2002-02-12 |
Multiprocessor system bus with cache state and LRU snoop responses for read/castout (RCO) address transaction
Grant 6,343,347 - Arimilli , et al. January 29, 2 | 2002-01-29 |
System bus directory snooping mechanism for read/castout (RCO) address transaction
Grant 6,343,344 - Arimilli , et al. January 29, 2 | 2002-01-29 |
Cache coherency protocol having tagged state used with cross-bars
Grant 6,341,336 - Arimilli , et al. January 22, 2 | 2002-01-22 |
Cache coherency protocols with global and local posted operations
Grant 6,330,643 - Arimilli , et al. December 11, 2 | 2001-12-11 |
Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data
Grant 6,321,305 - Arimilli , et al. November 20, 2 | 2001-11-20 |
Multiprocessor system bus with combined snoop responses implicitly updating snooper LRU position
Grant 6,279,086 - Arimilli , et al. August 21, 2 | 2001-08-21 |
Cache coherency protocol including an HR state
Grant 6,275,908 - Arimilli , et al. August 14, 2 | 2001-08-14 |
Multiprocessor system bus with system controller explicitly updating snooper cache state information
Grant 6,275,909 - Arimilli , et al. August 14, 2 | 2001-08-14 |
Cache coherency protocol having hovering (H), recent (R), and tagged (T) states
Grant 6,272,603 - Arimilli , et al. August 7, 2 | 2001-08-07 |
Cache coherency protocol including a hovering (H) state having a precise mode and an imprecise mode
Grant 6,263,407 - Arimilli , et al. July 17, 2 | 2001-07-17 |
Cache coherency protocol with selectively implemented tagged state
Grant 6,247,098 - Arimilli , et al. June 12, 2 | 2001-06-12 |
Eviction override for larx-reserved addresses
Grant 6,212,605 - Arimilli , et al. April 3, 2 | 2001-04-03 |
Deallocation with cache update protocol (L2 evictions)
Grant 6,195,729 - Arimilli , et al. February 27, 2 | 2001-02-27 |
Cache coherency protocol for a data processing system including a multi-level memory hierarchy
Grant 6,192,451 - Arimilli , et al. February 20, 2 | 2001-02-20 |
High performance cache directory addressing scheme for variable cache sizes utilizing associativity
Grant 6,192,458 - Arimilli , et al. February 20, 2 | 2001-02-20 |
Demand-based issuance of cache operations to a system bus
Grant 6,182,201 - Arimilli , et al. January 30, 2 | 2001-01-30 |
Demand based sync bus operation
Grant 6,175,930 - Arimilli , et al. January 16, 2 | 2001-01-16 |
Latch-and-hold circuit that permits subcircuits of an integrated circuit to operate at different frequencies
Grant 6,161,189 - Arimilli , et al. December 12, 2 | 2000-12-12 |
Cache coherency protocols with posted operations and tagged coherency states
Grant 6,145,059 - Arimilli , et al. November 7, 2 | 2000-11-07 |
Cache coherency protocol with independent implementation of optimized cache operations
Grant 6,141,733 - Arimilli , et al. October 31, 2 | 2000-10-31 |
Forward progress on retried snoop hits by altering the coherency state of a local cache
Grant 6,138,218 - Arimilli , et al. October 24, 2 | 2000-10-24 |
Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles
Grant 6,128,707 - Arimilli , et al. October 3, 2 | 2000-10-03 |
Dynamic folding of cache operations for multiple coherency-size systems
Grant 6,105,112 - Arimilli , et al. August 15, 2 | 2000-08-15 |
Demand based sync bus operation
Grant 6,065,086 - Arimilli , et al. May 16, 2 | 2000-05-16 |
Apparatus and method for separately layering cache and architectural specific functions in different operational controllers
Grant 6,061,762 - Arimilli , et al. May 9, 2 | 2000-05-09 |
Software-managed programmable unified/split caching mechanism for instructions and data
Grant 6,058,456 - Arimilli , et al. May 2, 2 | 2000-05-02 |
Method and system for assigning cache memory utilization within a symmetric multiprocessor data-processing system
Grant 6,038,642 - Arimilli , et al. March 14, 2 | 2000-03-14 |
Precise synchronization mechanism for SMP system buses using tagged snoop operations to avoid retries
Grant 6,029,204 - Arimilli , et al. February 22, 2 | 2000-02-22 |
Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels
Grant 6,026,470 - Arimilli , et al. February 15, 2 | 2000-02-15 |
Cache coherency protocol with efficient write-through aliasing
Grant 6,021,468 - Arimilli , et al. February 1, 2 | 2000-02-01 |
Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states
Grant 6,018,791 - Arimilli , et al. January 25, 2 | 2000-01-25 |
Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels
Grant 5,978,888 - Arimilli , et al. November 2, 1 | 1999-11-02 |
Optimizing a cache eviction mechanism by selectively introducing different levels of randomness into a replacement algorithm
Grant 5,974,507 - Arimilli , et al. October 26, 1 | 1999-10-26 |
Cache intervention from a cache line exclusively holding an unmodified value
Grant 5,963,974 - Arimilli , et al. October 5, 1 | 1999-10-05 |
Cache array defect functional bypassing using repair mask
Grant 5,958,068 - Arimilli , et al. September 28, 1 | 1999-09-28 |
System utilizing mastering and snooping circuitry that operate in response to clock signals having different frequencies generated by the communication controller
Grant 5,958,011 - Arimilli , et al. September 28, 1 | 1999-09-28 |
Shared intervention protocol for SMP bus using caches, snooping, tags and prioritizing
Grant 5,946,709 - Arimilli , et al. August 31, 1 | 1999-08-31 |
Shared memory-access priorization method for multiprocessors using caches and snoop responses
Grant 5,940,864 - Arimilli , et al. August 17, 1 | 1999-08-17 |
Cache intervention from only one of many cache lines sharing an unmodified value
Grant 5,940,856 - Arimilli , et al. August 17, 1 | 1999-08-17 |
Method and system for controlling access to a shared resource in a data processing system utilizing pseudo-random priorities
Grant 5,935,234 - Arimilli , et al. August 10, 1 | 1999-08-10 |
Method and system for controlling access to a shared resource that each requestor is concurrently assigned at least two pseudo-random priority weights
Grant 5,931,924 - Arimilli , et al. August 3, 1 | 1999-08-03 |
Method and system for speculatively sourcing cache memory data prior to upstream cache invalidation within a multiprocessor data-processing system
Grant 5,924,118 - Arimilli , et al. July 13, 1 | 1999-07-13 |
Adaptive writeback of cache line data in a computer operated with burst mode transfer cycles
Grant 5,924,121 - Arimilli , et al. July 13, 1 | 1999-07-13 |
Cache block store instruction operations where cache coherency is achieved without writing all the way back to main memory
Grant 5,909,698 - Arimilli , et al. June 1, 1 | 1999-06-01 |
Method and system for controlling access to a shared resource in a data processing system utilizing dynamically-determined weighted pseudo-random priorities
Grant 5,896,539 - Arimilli , et al. April 20, 1 | 1999-04-20 |
Demand-based larx-reserve protocol for SMP system buses
Grant 5,895,495 - Arimilli , et al. April 20, 1 | 1999-04-20 |
Method and system for back-end gathering of store instructions within a data-processing system
Grant 5,894,569 - Arimilli , et al. April 13, 1 | 1999-04-13 |
Method for recoverability via redundant cache arrays
Grant 5,883,904 - Arimilli , et al. March 16, 1 | 1999-03-16 |
Scalable symmetric multiprocessor data-processing system with data allocation among private caches and segments of system memory
Grant 5,860,101 - Arimilli , et al. January 12, 1 | 1999-01-12 |
Data processing system having demand based write through cache with enforced ordering
Grant 5,796,979 - Arimilli , et al. August 18, 1 | 1998-08-18 |
| 