Lewis; Jerry D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lewis; Jerry D..The latest application filed is for "data processing system, processor and method for claiming coherency ownership of a partial cache line of data".

Company Profile

0.12.9

Lewis; Jerry D. - Round Rock TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Claiming coherency ownership of a partial cache line of data Grant 8,255,635 - Arimilli , et al. August 28, 2	2012-08-28
Interconnect operation indicating acceptability of partial data delivery Grant 8,117,401 - Arimilli , et al. February 14, 2	2012-02-14
Cache management for partial cache line operations Grant 8,108,619 - Arimilli , et al. January 31, 2	2012-01-31
Performing dynamic request routing based on broadcast queue depths Grant 8,077,602 - Arimilli , et al. December 13, 2	2011-12-13
Partial cache line accesses based on memory access patterns Grant 8,024,527 - Arimilli , et al. September 20, 2	2011-09-20
Dynamic selection of a memory access size Grant 7,958,309 - Arimilli , et al. June 7, 2	2011-06-07
Cluster-wide system clock in a multi-tiered full-graph interconnect architecture Grant 7,921,316 - Arimilli , et al. April 5, 2	2011-04-05
System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture Grant 7,827,428 - Arimilli , et al. November 2, 2	2010-11-02
Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips Grant 7,779,148 - Arimilli , et al. August 17, 2	2010-08-17
Data Processing System, Processor And Method That Support Partial Cache Line Reads App 20090198960 - ARIMILLI; Lakshminarayana B. ; et al.	2009-08-06
Data Processing System, Processor And Method For Implementing Cache Management For Partial Cache Line Operations App 20090198912 - ARIMILLI; LAKSHMINARAYANA B. ; et al.	2009-08-06
Data Processing System, Processor And Method That Dynamically Select A Memory Access Size App 20090198915 - ARIMILLI; LAKSHMINARAYANA B. ; et al.	2009-08-06
System and Method for Performing Dynamic Request Routing Based on Broadcast Queue Depths App 20090198957 - Arimilli; Lakshminarayana B. ; et al.	2009-08-06
Data Processing System, Processor And Method In Which An Interconnect Operation Indicates Acceptability Of Partial Data Delivery App 20090198914 - ARIMILLI; LAKSHMINARAYANA B. ; et al.	2009-08-06
System and Method for Performing Dynamic Request Routing Based on Broadcast Source Request Information App 20090198958 - Arimilli; Lakshminarayana B. ; et al.	2009-08-06
Data Processing System, Processor And Method For Claiming Coherency Ownership Of A Partial Cache Line Of Data App 20090198911 - ARIMILLI; LAKSHMINARAYANA B. ; et al.	2009-08-06
Method for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture App 20090070617 - Arimilli; Lakshminarayana B. ; et al.	2009-03-12
System for Providing a Cluster-Wide System Clock in a Multi-Tiered Full-Graph Interconnect Architecture App 20090063886 - Arimilli; Lakshminarayana B. ; et al.	2009-03-05
Aborting an I/O operation started before all system data is received by the I/O controller after detecting a remote retry operation Grant 5,623,694 - Arimilli , et al. April 22, 1	1997-04-22
Coherency and synchronization mechanisms for I/O channel controllers in a data processing system Grant 5,613,153 - Arimilli , et al. March 18, 1	1997-03-18
Digital clock pulse positioning circuit for delaying a signal input by a fist time duration and a second time duration to provide a positioned clock signal Grant 5,548,797 - Arimilli , et al. August 20, 1	1996-08-20

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