Patent | Date |
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Lateral diffused metal oxide semiconductor field effect (LDMOS) transistor and device having LDMOS transistors Grant 11,127,855 - Sherman , et al. September 21, 2 | 2021-09-21 |
Oxide-nitride-oxide stack having multiple oxynitride layers Grant 10,903,342 - Levy , et al. January 26, 2 | 2021-01-26 |
Oxide-nitride-oxide stack having multiple oxynitride layers Grant 10,896,973 - Levy , et al. January 19, 2 | 2021-01-19 |
Lateral Diffused Metal Oxide Semiconductor Field Effect (ldmos) Transistor And Device Having Ldmos Transistors App 20200381553 - Sherman; Daniel ;   et al. | 2020-12-03 |
Radical Oxidation Process For Fabricating A Nonvolatile Charge Trap Memory Device App 20200287056 - Ramkumar; Krishnaswamy ;   et al. | 2020-09-10 |
Nonvolatile Charge Trap Memory Device Having A Deuterated Layer In A Multi-layer Charge-trapping Region App 20190319104 - Levy; Sagy ;   et al. | 2019-10-17 |
Oxide-nitride-oxide stack having multiple oxynitride layers Grant 10,374,067 - Levy , et al. | 2019-08-06 |
Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region Grant 10,263,087 - Levy , et al. | 2019-04-16 |
Apparatus of a metal-oxide-semiconductor (MOS) transistor including a multi-split gate Grant 10,217,826 - Kantarovsky , et al. Feb | 2019-02-26 |
Oxide-nitride-oxide Stack Having Multiple Oxynitride Layers App 20180366564 - Levy; Sagy ;   et al. | 2018-12-20 |
Oxide-nitride-oxide Stack Having Multiple Oxynitride Layers App 20180366563 - Levy; Sagy ;   et al. | 2018-12-20 |
Apparatus Of A Metal-oxide-semiconductor (mos) Transistor Including A Multi-split Gate App 20180145139 - Kantarovsky; Johnatan A. ;   et al. | 2018-05-24 |
Nonvolatile Charge Trap Memory Device Having A Deuterated Layer In A Multi-layer Charge-trapping Region App 20170352732 - Levy; Sagy ;   et al. | 2017-12-07 |
Semiconductor die with a metal via Grant 9,837,411 - Levin , et al. December 5, 2 | 2017-12-05 |
LDMOS device having a low angle sloped oxide Grant 9,812,566 - Levy , et al. November 7, 2 | 2017-11-07 |
Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate "bump" structure Grant 9,806,174 - Levy , et al. October 31, 2 | 2017-10-31 |
Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region Grant 9,741,803 - Levy , et al. August 22, 2 | 2017-08-22 |
Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region Grant 9,716,153 - Levy , et al. July 25, 2 | 2017-07-25 |
Semiconductor Die With A Metal Via App 20170018503 - Levin; Sharon ;   et al. | 2017-01-19 |
Double-resurf Ldmos With Drift And Psurf Implants Self-aligned To A Stacked Gate "bump" Structure App 20160372578 - Levy; Sagy ;   et al. | 2016-12-22 |
Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate "bump" structure Grant 9,484,454 - Levy , et al. November 1, 2 | 2016-11-01 |
Oxide-nitride-oxide Stack Having Multiple Oxynitride Layers App 20160308033 - LEVY; Sagy ;   et al. | 2016-10-20 |
Nonvolatile Charge Trap Memory Device Having A Deuterated Layer In A Multi-Layer Charge-Trapping Region App 20160308009 - LEVY; Sagy ;   et al. | 2016-10-20 |
Oxide-nitride-oxide stack having multiple oxynitride layers Grant 9,449,831 - Levy , et al. September 20, 2 | 2016-09-20 |
Nonvolatile charge trap memory device having a high dielectric constant blocking region Grant 9,431,549 - Polishchuk , et al. August 30, 2 | 2016-08-30 |
SONOS ONO stack scaling Grant 9,299,568 - Jenne , et al. March 29, 2 | 2016-03-29 |
Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure App 20150279969 - Levy; Sagy ;   et al. | 2015-10-01 |
Double RESURF LDMOS with separately patterned P+ and N+ buried layers formed by shared mask Grant 9,105,712 - Levy , et al. August 11, 2 | 2015-08-11 |
Method of fabricating a nonvolatile charge trap memory device Grant 8,993,453 - Ramkumar , et al. March 31, 2 | 2015-03-31 |
Radical oxidation process for fabricating a nonvolatile charge trap memory device Grant 8,940,645 - Ramkumar , et al. January 27, 2 | 2015-01-27 |
Integration of non-volatile charge trap memory devices and logic CMOS devices Grant 8,871,595 - Ramkumar , et al. October 28, 2 | 2014-10-28 |
Nonvolatile charge trap memory device having a high dielectric constant blocking region Grant 8,860,122 - Polishchuk , et al. October 14, 2 | 2014-10-14 |
Memory transistor with multiple charge storing layers and a high work function gate electrode Grant 8,859,374 - Polishchuk , et al. October 14, 2 | 2014-10-14 |
Sonos Type Stacks For Nonvolatile Changetrap Memory Devices And Methods To Form The Same App 20140103418 - PUCHNER; Helmut ;   et al. | 2014-04-17 |
Methods for fabricating semiconductor memory with process induced strain Grant 8,691,648 - Polishchuk , et al. April 8, 2 | 2014-04-08 |
Integration of non-volatile charge trap memory devices and logic CMOS devices Grant 8,679,927 - Ramkumar , et al. March 25, 2 | 2014-03-25 |
Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region Grant 8,680,601 - Levy , et al. March 25, 2 | 2014-03-25 |
Double-Resurf LDMOS With Drift And PSURF Implants Self-Aligned To A Stacked Gate "BUMP" Structure App 20140070315 - Levy; Sagy ;   et al. | 2014-03-13 |
Oxide-nitride-oxide stack having multiple oxynitride layers Grant 8,643,124 - Levy , et al. February 4, 2 | 2014-02-04 |
Nitridation oxidation of tunneling layer for improved SONOS speed and retention Grant 8,637,921 - Levy , et al. January 28, 2 | 2014-01-28 |
Memory transistor with multiple charge storing layers and a high work function gate electrode Grant 8,633,537 - Polishchuk , et al. January 21, 2 | 2014-01-21 |
Methods for fabricating semiconductor memory with process induced strain Grant 8,592,891 - Polishchuk , et al. November 26, 2 | 2013-11-26 |
Memory Transistor With Multiple Charge Storing Layers And A High Work Function Gate Electrode App 20130307053 - POLISHCHUK; Igor ;   et al. | 2013-11-21 |
Radical Oxidation Process For Fabricating A Nonvolatile Charge Trap Memory Device App 20130309826 - RAMKUMAR; Krishnaswamy ;   et al. | 2013-11-21 |
Nonvolatile Charge Trap Memory Device Having A Deuterated Layer In A Multi-Layer Charge-Trapping Region App 20130306975 - LEVY; Sagy ;   et al. | 2013-11-21 |
Sonos Ono Stack Scaling App 20130307052 - JENNE; Fredrick ;   et al. | 2013-11-21 |
Oxide-nitride-oxide Stack Having Multiple Oxynitride Layers App 20130175504 - Levy; Sagy ;   et al. | 2013-07-11 |
Nonvolatile Charge Trap Memory Device Having A High Dielectric Constant Blocking Region App 20130175604 - Polishchuk; Igor ;   et al. | 2013-07-11 |
Integration Of Non-volatile Charge Trap Memory Devices And Logic Cmos Devices App 20130178031 - Ramkumar; Krishnaswamy ;   et al. | 2013-07-11 |
Method of fabricating a nonvolatile charge trap memory device Grant 8,318,608 - Ramkumar , et al. November 27, 2 | 2012-11-27 |
SONOS type stacks for nonvolatile change trap memory devices and methods to form the same Grant 8,163,660 - Puchner , et al. April 24, 2 | 2012-04-24 |
Integration of non-volatile charge trap memory devices and logic CMOS devices Grant 8,093,128 - Koutny, Jr. , et al. January 10, 2 | 2012-01-10 |
Sequential deposition and anneal of a dielectic layer in a charge trapping memory device Grant 8,088,683 - Ramkumar , et al. January 3, 2 | 2012-01-03 |
Oxynitride bilayer formed using a precursor inducing a high charge trap density in a top layer of the bilayer Grant 8,067,284 - Levy November 29, 2 | 2011-11-29 |
Memory transistor with multiple charge storing layers and a high work function gate electrode Grant 8,063,434 - Polishchuk , et al. November 22, 2 | 2011-11-22 |
Oxide-Nitride-Oxide Stack Having Multiple Oxynitride Layers App 20110248332 - Levy; Sagy ;   et al. | 2011-10-13 |
Trapped-charge non-volatile memory with uniform multilevel programming Grant 7,898,852 - Levy , et al. March 1, 2 | 2011-03-01 |
Nonvolatile charge trap memory device having <100> crystal plane channel orientation Grant 7,880,219 - Polishchuk , et al. February 1, 2 | 2011-02-01 |
Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices Grant 7,799,670 - Ramkumar , et al. September 21, 2 | 2010-09-21 |
Single-wafer process for fabricating a nonvolatile charge trap memory device Grant 7,670,963 - Ramkumar , et al. March 2, 2 | 2010-03-02 |
SONOS Type Stacks for Nonvolatile ChangeTrap Memory Devices and Methods to Form the Same App 20100041222 - Puchner; Helmut ;   et al. | 2010-02-18 |
Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices App 20090242962 - Ramkumar; Krishnaswamy ;   et al. | 2009-10-01 |
Sequential deposition and anneal of a dielectic layer in a charge trapping memory device App 20090243001 - Ramkumar; Krishnaswamy ;   et al. | 2009-10-01 |
Oxide-nitride-oxide stack having multiple oxynitride layers App 20090179253 - Levy; Sagy ;   et al. | 2009-07-16 |
Nonvolatile Charge Trap Memory Device Having A High Dielectric Constant Blocking Region App 20090152621 - Polishchuk; Igor ;   et al. | 2009-06-18 |
Nitridation oxidation of tunneling layer for improved SONOS speed and retention App 20090032863 - Levy; Sagy ;   et al. | 2009-02-05 |
Radical Oxidation Process For Fabricating A Nonvolatile Charge Trap Memory Device App 20090011609 - Ramkumar; Krishnaswamy ;   et al. | 2009-01-08 |
Integration Of Non-volatile Charge Trap Memory Devices And Logic Cmos Devices App 20080296664 - Ramkumar; Krishnaswamy ;   et al. | 2008-12-04 |
Nonvolatile charge trap memory device having a deuterated layer in a multi-layer charge-trapping region App 20080290399 - Levy; Sagy ;   et al. | 2008-11-27 |
Nonvolatile charge trap memory device having <100> crystal plane channel orientation App 20080290398 - Polishchuk; Igor ;   et al. | 2008-11-27 |
SONOS ONO stack scaling App 20080290400 - Jenne; Fredrick B. ;   et al. | 2008-11-27 |
Single-wafer process for fabricating a nonvolatile charge trap memory device App 20080293254 - Ramkumar; Krishnaswamy ;   et al. | 2008-11-27 |
Integration Of Non-volatile Charge Trap Memory Devices And Logic Cmos Devices App 20080293207 - Koutny, JR.; William W.C. ;   et al. | 2008-11-27 |
Silicon nitride films Grant 7,446,063 - Levy , et al. November 4, 2 | 2008-11-04 |
Method for depositing a coating having a relatively high dielectric constant onto a substrate App 20060110531 - Chang; Jane P. ;   et al. | 2006-05-25 |
Method for depositing a coating having a relatively high dielectric constant onto a substrate Grant 6,884,719 - Chang , et al. April 26, 2 | 2005-04-26 |
Method of forming dielectric films Grant 6,638,876 - Levy , et al. October 28, 2 | 2003-10-28 |
Method for depositing a coating having a relatively high dielectric constant onto a substrate App 20030031793 - Chang, Jane P. ;   et al. | 2003-02-13 |
Method of forming dielectric films App 20020142624 - Levy, Sagy ;   et al. | 2002-10-03 |
UV pretreatment process for ultra-thin oxynitride formation Grant 6,451,713 - Tay , et al. September 17, 2 | 2002-09-17 |
Semiconductor wafer pretreatment utilizing ultraviolet activated chlorine Grant 6,204,120 - Gilboa , et al. March 20, 2 | 2001-03-20 |
Selective hemispherical grain silicon deposition Grant 6,191,011 - Gilboa , et al. February 20, 2 | 2001-02-20 |