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Method, system, and computer program product for implementing prototyping and floorplanning of electronic circuit designs
Grant 9,760,667 - Levitsky , et al. September 12, 2 | 2017-09-12 |
Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs
Grant 9,165,098 - Bhardwaj , et al. October 20, 2 | 2015-10-20 |
Multi-phase models for timing closure of integrated circuit designs
Grant 9,152,742 - Gupta , et al. October 6, 2 | 2015-10-06 |
Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design data
Grant 9,141,740 - Liu , et al. September 22, 2 | 2015-09-22 |
Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs
Grant 9,053,270 - Singh , et al. June 9, 2 | 2015-06-09 |
Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints
Grant 8,977,994 - Levitsky , et al. March 10, 2 | 2015-03-10 |
Timing budgeting of nested partitions for hierarchical integrated circuit designs
Grant 8,977,995 - Arora , et al. March 10, 2 | 2015-03-10 |
Methods for single pass parallel hierarchical timing closure of integrated circuit designs
Grant 8,935,642 - Bhardwaj , et al. January 13, 2 | 2015-01-13 |
Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs
Grant 8,769,455 - Singh , et al. July 1, 2 | 2014-07-01 |
Methods for generating a user interface for timing budget analysis of integrated circuit designs
Grant 8,745,560 - Bhardwaj , et al. June 3, 2 | 2014-06-03 |
Method and system for implementing clock tree prototyping
Grant 8,719,743 - Kollaritsch , et al. May 6, 2 | 2014-05-06 |
Multi-phase models for timing closure of integrated circuit designs
Grant 8,640,066 - Gupta , et al. January 28, 2 | 2014-01-28 |
Common path pessimism removal for hierarchical timing analysis
Grant 8,572,532 - Singh , et al. October 29, 2 | 2013-10-29 |
Systems for single pass parallel hierarchical timing closure of integrated circuit designs
Grant 8,539,402 - Bhardwaj , et al. September 17, 2 | 2013-09-17 |
User interface for timing budget analysis of integrated circuit designs
Grant 8,504,978 - Bhardwaj , et al. August 6, 2 | 2013-08-06 |
Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs
Grant 8,365,113 - Bhardwaj , et al. January 29, 2 | 2013-01-29 |
Methods, Systems, And Articles Of Manufacture For Implementing Full-chip Optimization With Reduced Physical Design Data
App 20120254818 - Liu; Dongzi ; et al. | 2012-10-04 |
System and method of computing pin criticalities under process variations for timing analysis and optimization
Grant 8,151,229 - Chang , et al. April 3, 2 | 2012-04-03 |
Method and system for implementing timing analysis and optimization of an electronic design based upon extended regions of analysis
Grant 7,930,675 - Levitsky , et al. April 19, 2 | 2011-04-19 |
System and method of generating hierarchical block-level timing constraints from chip-level timing constraints
Grant 7,926,011 - Levitsky , et al. April 12, 2 | 2011-04-12 |
Method And System For Implementing Timing Analysis And Optimization Of An Electronic Design Based Upon Extended Regions Of Analysis
App 20090172619 - Levitsky; Oleg ; et al. | 2009-07-02 |
Optimization Of Timing Models Using Bus Compression
App 20040111247 - Berevoescu, Paul ; et al. | 2004-06-10 |
Unified timing analysis for model interface layout parasitics
Grant 6,704,697 - Berevoescu , et al. March 9, 2 | 2004-03-09 |
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