Levi; Amitay

Patent Applications and Registrations

Patent applications and USPTO patent grants for Levi; Amitay.The latest application filed is for "compact and efficient cmos inverter".

Company Profile

50.59.63

Levi; Amitay - Cupertino CA
Levi; Amitay - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Selector transistor with metal replacement gate wordline Grant 11,444,123 - Beery , et al. September 13, 2	2022-09-13
Compact And Efficient Cmos Inverter App 20220189829 - Levi; Amitay ; et al.	2022-06-16
Dram With Selective Epitaxial Cell Transistor App 20220189961 - Walker; Andrew J. ; et al.	2022-06-16
High density 3D magnetic random access memory (MRAM) cell integration using wafer cut and transfer Grant 11,342,498 - Gajek , et al. May 24, 2	2022-05-24
DRAM with selective epitaxial transistor and buried bitline Grant 11,329,048 - Walker , et al. May 10, 2	2022-05-10
Compact and efficient CMOS inverter Grant 11,302,586 - Levi , et al. April 12, 2	2022-04-12
DRAM with selective epitaxial cell transistor Grant 11,302,697 - Walker , et al. April 12, 2	2022-04-12
Perpendicular magnetic tunnel junction memory cells having vertical channels Grant 11,222,970 - Kim , et al. January 11, 2	2022-01-11
Selector Transistor With Metal Replacement Gate Wordline App 20210391386 - Beery; Dafna ; et al.	2021-12-16
Compact And Efficient Cmos Inverter App 20210305105 - Levi; Amitay ; et al.	2021-09-30
Dram With Selective Epitaxial Transistor And Buried Bitline App 20210305256 - Walker; Andrew J. ; et al.	2021-09-30
Dram With Selective Epitaxial Cell Transistor App 20210233913 - Walker; Andrew J. ; et al.	2021-07-29
Selector Transistor With Continuously Variable Current Drive App 20210217814 - Walker; Andrew J. ; et al.	2021-07-15
Integration Of Epitaxially Grown Channel Selector With Two Terminal Resistive Switching Memory Element App 20210090626 - Beery; Dafna ; et al.	2021-03-25
Integration of epitaxially grown channel selector with two terminal resistive switching memory element Grant 10,957,370 - Beery , et al. March 23, 2	2021-03-23
Integration Of Epitaxially Grown Channel Selector With Mram Device App 20210065760 - Beery; Dafna ; et al.	2021-03-04
Integration of epitaxially grown channel selector with MRAM device Grant 10,937,479 - Beery , et al. March 2, 2	2021-03-02
Vertically-strained silicon device for use with a perpendicular magnetic tunnel junction (PMTJ) Grant 10,916,582 - Kim , et al. February 9, 2	2021-02-09
Fabricating Sub-Lithographic Devices App 20200409272 - Sharma; Gian ; et al.	2020-12-31
Fabricating Devices with Reduced Isolation Regions App 20200409273 - Levi; Amitay ; et al.	2020-12-31
Adjustable current selectors Grant 10,854,260 - Kim , et al. December 1, 2	2020-12-01
Flexible substrate for use with a perpendicular magnetic tunnel junction (PMTJ) Grant 10,790,333 - Kim , et al. September 29, 2	2020-09-29
Methods of fabricating dual threshold voltage devices Grant 10,770,561 - Sharma , et al. Sep	2020-09-08
Dual threshold voltage devices having a first transistor and a second transistor Grant 10,770,510 - Sharma , et al. Sep	2020-09-08
Shared bit line array architecture for magnetoresistive memory Grant 10,679,685 - Hoang , et al.	2020-06-09
Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels Grant 10,658,425 - Kim , et al.	2020-05-19
Memory Cell Using Selective Epitaxial Vertical Channel Mos Selector Transistor App 20200127052 - Walker; Andrew J. ; et al.	2020-04-23
Method of making a three dimensional perpendicular magnetic tunnel junction with thin-film transistor Grant 10,629,649 - Kim , et al.	2020-04-21
Patterning of high density small feature size pillar structures Grant 10,614,867 - Sharma , et al.	2020-04-07
Patterning Of High Density Small Feature Size Pillar Structures App 20200043537 - Sharma; Gian ; et al.	2020-02-06
Dual gate memory devices Grant 10,497,415 - Kim , et al. De	2019-12-03
Three Dimensional Perpendicular Magnetic Tunnel Junction With Thin Film Transistor Array App 20190355896 - Kim; Kuk-Hwan ; et al.	2019-11-21
Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels Grant 10,468,293 - Kim , et al. No	2019-11-05
Perpendicular magnetic tunnel junction memory cells having shared source contacts Grant 10,460,778 - Kim , et al. Oc	2019-10-29
Methods of Fabricating Dual Threshold Voltage Devices App 20190311956 - Sharma; Gian ; et al.	2019-10-10
Methods of fabricating magnetic tunnel junctions integrated with selectors Grant 10,438,996 - Kim , et al. O	2019-10-08
Annular vertical Si etched channel MOS devices Grant 10,438,999 - Sharma , et al. O	2019-10-08
Dual channel/gate vertical field-effect transistor (FET) for use with a perpendicular magnetic tunnel junction (PMTJ) Grant 10,431,628 - Kim , et al. O	2019-10-01
Adjustable Current Selectors App 20190287596 - Kim; Kuk-Hwan ; et al.	2019-09-19
Three dimensional perpendicular magnetic junction with thin-film transistor Grant 10,355,045 - Kim , et al. July 16, 2	2019-07-16
Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ) Grant 10,355,046 - Kim , et al. July 16, 2	2019-07-16
Fabrication methods of forming annular vertical SI etched channel MOS devices Grant 10,355,047 - Sharma , et al. July 16, 2	2019-07-16
Methods Of Fabricating Magnetic Tunnel Junctions Integrated With Selectors App 20190214430 - KIM; Kuk-Hwan ; et al.	2019-07-11
Dual Threshold Voltage Devices App 20190214431 - Sharma; Gian ; et al.	2019-07-11
Dual Gate Memory Devices App 20190214069 - Kim; Kuk-Hwan ; et al.	2019-07-11
High Density 3d Magnetic Random Access Memory (mram) Cell Integration Using Wafer Cut And Transfer App 20190214552 - Gajek; Marcin ; et al.	2019-07-11
Dual Channel/gate Vertical Field-effect Transistor (fet) For Use With A Perpendicular Magnetic Tunnel Junction (pmtj) App 20190214432 - Kim; Kuk-Hwan ; et al.	2019-07-11
Fabrication Of A Perpendicular Magnetic Tunnel Junction (pmtj) Using Block Copolymers App 20190214551 - Kim; Kuk-Hwan ; et al.	2019-07-11
Fabrication methods of forming cylindrical vertical SI etched channel 3D switching devices Grant 10,347,822 - Sharma , et al. July 9, 2	2019-07-09
Cylindrical vertical SI etched channel 3D switching devices Grant 10,347,311 - Sharma , et al. July 9, 2	2019-07-09
Methods Of Forming Perpendicular Magnetic Tunnel Junction Memory Cells Having Vertical Channels App 20190206941 - Kim; Kuk-Hwan ; et al.	2019-07-04
Vertical Compound Semiconductor For Use With A Perpendicular Magnetic Tunnel Junction (pmtj) App 20190207098 - Kim; Kuk-Hwan ; et al.	2019-07-04
Fabrication Methods Of Forming Cylindrical Vertical Si Etched Channel 3d Switching Devices App 20190207081 - Sharma; Gian ; et al.	2019-07-04
Flexible Substrate For Use With A Perpendicular Magnetic Tunnel Junction (pmtj) App 20190206933 - Kim; Kuk-Hwan ; et al.	2019-07-04
Method Of Making A Three Dimensional Perpendicular Magnetic Tunnel Junction With Thin-film Transistor App 20190206932 - Kim; Kuk-Hwan ; et al.	2019-07-04
Cylindrical Vertical Si Etched Channel 3d Switching Devices App 20190206461 - Sharma; Gian ; et al.	2019-07-04
Perpendicular Magnetic Tunnel Junction Memory Cells Having Shared Source Contacts App 20190206463 - Kim; Kuk-Hwan ; et al.	2019-07-04
Methods Of Forming Perpendicular Magnetic Tunnel Junction Memory Cells Having Vertical Channels App 20190206716 - Kim; Kuk-Hwan ; et al.	2019-07-04
Three Dimensional Perpendicular Magnetic Junction With Thin-film Transistor App 20190206934 - Kim; Kuk-Hwan ; et al.	2019-07-04
Vertically-strained Silicon Device For Use With A Perpendicular Magnetic Tunnel Junction (pmtj) App 20190206940 - Kim; Kuk-Hwan ; et al.	2019-07-04
Perpendicular Magnetic Tunnel Junction Memory Cells Having Vertical Channels App 20190207024 - Kim; Kuk-Hwan ; et al.	2019-07-04
Annular Vertical Si Etched Channel Mos Devices App 20190206938 - Sharma; Gian ; et al.	2019-07-04
Fabrication Methods Of Forming Annular Vertical Si Etched Channel Mos Devices App 20190206937 - Sharma; Gian ; et al.	2019-07-04
Vertical Steep-Slope Field-Effect Transistor (I-MOSFET) with Offset Gate Electrode for Driving a Perpendicular Magnetic Tunnel J App 20190206935 - Kim; Kuk-Hwan ; et al.	2019-07-04
Shared Bit Line Array Architecture For Magnetoresistive Memory App 20190198078 - HOANG; Loc ; et al.	2019-06-27
Fabrication of a perpendicular magnetic tunnel junction (PMTJ) using block copolymers Grant 10,333,063 - Kim , et al.	2019-06-25
Adjustable current selectors Grant 10,319,424 - Kim , et al.	2019-06-11
Steep slope field-effect transistor (FET) for a perpendicular magnetic tunnel junction (PMTJ) Grant 10,243,021 - Kim , et al.	2019-03-26
Predicting tunnel barrier endurance using redundant memory structures Grant 10,236,075 - Kim , et al.	2019-03-19
Methods of fabricating contacts for cylindrical devices Grant 10,192,787 - Sharma , et al. Ja	2019-01-29
Methods of fabricating dual threshold voltage devices with stacked gates Grant 10,192,788 - Sharma , et al. Ja	2019-01-29
Methods of fabricating dual threshold voltage devices Grant 10,192,789 - Sharma , et al. Ja	2019-01-29
Dual threshold voltage devices with stacked gates Grant 10,192,984 - Sharma , et al. Ja	2019-01-29
Buried tap for a vertical transistor used with a perpendicular magnetic tunnel junction (PMTJ) Grant 10,186,551 - Kim , et al. Ja	2019-01-22
Memory devices with magnetic random access memory (MRAM) cells and associated structures for connecting the MRAM cells Grant 9,054,029 - Berger , et al. June 9, 2	2015-06-09
Magnetic random access memory cells having improved size and shape characteristics Grant 8,962,493 - Levi , et al. February 24, 2	2015-02-24
Memory Devices with Magnetic Random Access Memory (MRAM) Cells and Associated Structures for Connecting the MRAM Cells App 20140361392 - Berger; Neal ; et al.	2014-12-11
Memory devices with magnetic random access memory (MRAM) cells and associated structures for connecting the MRAM cells Grant 8,816,455 - Berger , et al. August 26, 2	2014-08-26
Memory Devices with Magnetic Random Access Memory (MRAM) Cells and Associated Structures for connecting the MRAM Cells App 20140110802 - Berger; Neal ; et al.	2014-04-24
High endurance non-volatile memory cell and array Grant 8,384,147 - Do , et al. February 26, 2	2013-02-26
High Endurance Non-volatile Memory Cell And Array App 20120273864 - Do; Nhan ; et al.	2012-11-01
Magnetic Random Access Memory Cells Having Improved Size And Shape Characteristics App 20120146166 - LEVI; AMITAY ; et al.	2012-06-14
Non-volatile memory cell with self aligned floating and erase gates, and method of making same Grant 8,148,768 - Do , et al. April 3, 2	2012-04-03
Self-aligned method of forming a semiconductor memory array of floating memory cells with source side erase, and a memory array made thereby Grant 8,138,524 - Kotov , et al. March 20, 2	2012-03-20
Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing App 20110127599 - Liu; Xian ; et al.	2011-06-02
Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing Grant 7,927,994 - Liu , et al. April 19, 2	2011-04-19
Split Gate Non-volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing App 20110076816 - Liu; Xian ; et al.	2011-03-31
Split gate non-volatile flash memory cell having a floating gate, control gate, select gate and an erase gate with an overhang over the floating gate, array and method of manufacturing Grant 7,868,375 - Liu , et al. January 11, 2	2011-01-11
Non-volatile memory cell with buried select gate, and method of making same Grant 7,851,846 - Do , et al. December 14, 2	2010-12-14
Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates Grant 7,829,404 - Klinger , et al. November 9, 2	2010-11-09
Semiconductor memory array of floating gate memory cells with program/erase and select gates Grant 7,816,723 - Klinger , et al. October 19, 2	2010-10-19
Non-volatile Memory Cell With Buried Select Gate, And Method Of Making Same App 20100133602 - Do; Nhan ; et al.	2010-06-03
Non-volatile Memory Cell With Self Aligned Floating And Erase Gates, And Method Of Making Same App 20100127308 - Do; Nhan ; et al.	2010-05-27
Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing App 20100054043 - Liu; Xian ; et al.	2010-03-04
Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing App 20090039410 - Liu; Xian ; et al.	2009-02-12
Self-aligned method of forming a semiconductor memory array of floating gate memory cells with source side erase, and a memory array made thereby App 20080099789 - Kotov; Alexander ; et al.	2008-05-01
Semiconductor Memory Array Of Floating Gate Memory Cells With Program/erase And Select Gates App 20080083945 - Klinger; Pavel ; et al.	2008-04-10
Method Of Making And Operating A Semiconductor Memory Array Of Floating Gate Memory Cells With Program/erase And Select Gates App 20080084744 - Klinger; Pavel ; et al.	2008-04-10
Semiconductor memory array of floating gate memory cells with program/erase and select gates Grant 7,315,056 - Klinger , et al. January 1, 2	2008-01-01
Method of merging designs of an integrated circuit from a plurality of sources App 20070288881 - Maheshwarla; Sreeni ; et al.	2007-12-13
Non-volatile memory cell in a trench having a first portion deeper than a second portion, an array of such memory cells, and method of manufacturing App 20070215931 - Kianian; Sohrab ; et al.	2007-09-20
Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing Grant 7,227,217 - Levi , et al. June 5, 2	2007-06-05
Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system Grant 7,149,110 - Tran , et al. December 12, 2	2006-12-12
Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric Grant 7,084,453 - Chern , et al. August 1, 2	2006-08-01
Semiconductor memory array of floating gate memory cells with program/erase and select gates, and methods of making and operating same App 20050269622 - Klinger, Pavel ; et al.	2005-12-08
Method of planarizing a semiconductor die Grant 6,969,687 - Levi , et al. November 29, 2	2005-11-29
Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing App 20050213386 - Levi, Amitay ; et al.	2005-09-29
Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling Grant 6,855,980 - Wang , et al. February 15, 2	2005-02-15
Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing App 20050012137 - Levi, Amitay ; et al.	2005-01-20
Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dieletric App 20040212007 - Chern, Geeng-Chuan ; et al.	2004-10-28
Method of forming a semiconductor array of floating gate memory cells and strap regions Grant 6,773,974 - Wang , et al. August 10, 2	2004-08-10
Method of planarizing a semiconductor die App 20040152397 - Levi, Amitay ; et al.	2004-08-05
Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system App 20040125653 - Tran, Hieu Van ; et al.	2004-07-01
Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling App 20040084717 - Wang, Chih Hsin ; et al.	2004-05-06
Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling Grant 6,727,545 - Wang , et al. April 27, 2	2004-04-27
Method of planarizing a semiconductor die Grant 6,703,318 - Levi , et al. March 9, 2	2004-03-09
Method of forming a semiconductor array of floating gate memory cells and strap regions App 20030189223 - Wang, Chih Hsin ; et al.	2003-10-09
Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric App 20030102504 - Chern, Geeng-Chuan ; et al.	2003-06-05
Seniconductor Array Of Floating Gate Memory Cells And Strap Regions App 20030080371 - Wang, Chih Hsin ; et al.	2003-05-01
Self aligned method of forming a semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling, and a memory array made thereby App 20020034849 - Wang, Chih Hsin ; et al.	2002-03-21