LEVERD; Francois

Patent Applications and Registrations

Patent applications and USPTO patent grants for LEVERD; Francois.The latest application filed is for "method for forming a capacitive isolation trench and substrate comprising such a trench".

Company Profile

2.12.16

LEVERD; Francois - Saint Ismier FR
LEVERD; Francois - St. Ismier FR
Leverd, Francois - St-lsmier FR
Leverd; Francois - Cesson FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method For Forming A Capacitive Isolation Trench And Substrate Comprising Such A Trench App 20220028726 - MONNIER; Denis ; et al.	2022-01-27
Method of etching a cavity in a stack of layers Grant 10,770,306 - Bar , et al. Sep	2020-09-08
Etching Method App 20200211835 - RISTOIU; Delia ; et al.	2020-07-02
Method Of Etching A Cavity In A Stack Of Layers App 20190214270 - BAR; Pierre ; et al.	2019-07-11
Process for fabricating a backside-illuminated imaging device and corresponding device Grant 8,847,344 - Roy , et al. September 30, 2	2014-09-30
Method for producing a deep trench in a microelectronic component substrate Grant 8,796,148 - Leverd , et al. August 5, 2	2014-08-05
Method For Forming A Deep Trench In A Microelectronic Component Substrate App 20130154051 - Tournier; Arnaud ; et al.	2013-06-20
Method for forming a back-side illuminated image sensor Grant 8,436,440 - Marty , et al. May 7, 2	2013-05-07
Method For Producing A Deep Trench In A Microelectronic Component Substrate App 20130052829 - Leverd; Francois ; et al.	2013-02-28
Process For Fabricating A Backside-illuminated Imaging Device And Corresponding Device App 20120306035 - Roy; Francois ; et al.	2012-12-06
Method For Forming A Back-side Illuminated Image Sensor App 20110108939 - Marty; Michel ; et al.	2011-05-12
Method for forming a strongly-conductive buried layer in a semiconductor substrate Grant 7,456,071 - Marty , et al. November 25, 2	2008-11-25
Electronic components and method of fabricating the same Grant 7,214,597 - Coronel , et al. May 8, 2	2007-05-08
Integrated circuit with a strongly-conductive buried layer App 20050191818 - Marty, Michel ; et al.	2005-09-01
Isolating trench and manufacturing process Grant 6,828,646 - Marty , et al. December 7, 2	2004-12-07
Buried connections in an integrated circuit substrate App 20040145058 - Marty, Michel ; et al.	2004-07-29
Integrated circuit with a strongly-conductive buried layer App 20040104448 - Marty, Michel ; et al.	2004-06-03
Electronic components and method of fabricating the same App 20040033676 - Coronel, Philippe ; et al.	2004-02-19
Method for production process for the local interconnection level using a dielectric conducting pair on pair Grant 6,689,655 - Coronel , et al. February 10, 2	2004-02-10
Isolating trench and manufacturing process App 20030098493 - Marty, Michel ; et al.	2003-05-29
Production process for the local interconnection level using a dielectric-conducting pair on grid App 20020142519 - Coronel, Philippe ; et al.	2002-10-03
Dram memory integration method App 20020110976 - Coronel, Philippe ; et al.	2002-08-15
Process for forming deep and shallow insulative regions of an integrated circuit App 20020014676 - Marty, Michel ; et al.	2002-02-07
Method for buried plate formation in deep trench capacitors Grant 6,281,068 - Coronel , et al. August 28, 2	2001-08-28

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