loadpatents
name:-0.053972005844116
name:-0.072738885879517
name:-0.0072329044342041
Leventis; Paul Patent Filings

Leventis; Paul

Patent Applications and Registrations

Patent applications and USPTO patent grants for Leventis; Paul.The latest application filed is for "methods and systems for rendering and encoding content for online interactive gaming sessions".

Company Profile
4.44.28
  • Leventis; Paul - Toronto CA
  • Leventis; Paul - Mountain View CA
  • Leventis; Paul - Ontario CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Methods and systems for rendering and encoding content for online interactive gaming sessions
Grant 11,369,873 - Smullen , et al. June 28, 2
2022-06-28
Methods And Systems For Rendering And Encoding Content For Online Interactive Gaming Sessions
App 20220054940 - Smullen; Clinton ;   et al.
2022-02-24
Methods and systems for rendering and encoding content for online interactive gaming sessions
Grant 11,198,065 - Smullen , et al. December 14, 2
2021-12-14
Shadow Tracking Of Real-time Interactive Simulations For Complex System Analysis
App 20210365328 - Zimring; Dov ;   et al.
2021-11-25
Memory management in gaming rendering
Grant 11,110,348 - Lalonde , et al. September 7, 2
2021-09-07
Resolution-based scaling of real-time interactive graphics
Grant 11,077,364 - Zimring , et al. August 3, 2
2021-08-03
Resolution-based Scaling Of Real-time Interactive Graphics
App 20210220733 - Zimring; Dov ;   et al.
2021-07-22
Memory Management In Gaming Rendering
App 20210213354 - Lalonde; Paul ;   et al.
2021-07-15
Methods and Systems for Rendering and Encoding Content for Online Interactive Gaming Sessions
App 20200238175 - Smullen; Clinton ;   et al.
2020-07-30
Distributed Sample-based Game Profiling With Game Metadata And Metrics And Gaming Api Platform Supporting Third-party Content
App 20200230499 - Buser; Jack ;   et al.
2020-07-23
Resolution-Based Scaling of Real-time Interactive Graphics
App 20190321725 - Zimring; Dov ;   et al.
2019-10-24
Memory Management in Gaming Rendering
App 20190308099 - Lalonde; Paul ;   et al.
2019-10-10
PLD architecture for flexible placement of IP function blocks
Grant 9,094,014 - Lee , et al. July 28, 2
2015-07-28
Pld Architecture For Flexible Placement Of Ip Function Blocks
App 20140210515 - Lee; Andy L. ;   et al.
2014-07-31
PLD architecture for flexible placement of IP function blocks
Grant 8,732,646 - Lee , et al. May 20, 2
2014-05-20
Simultaneous switching noise optimization
Grant 8,694,946 - Fender , et al. April 8, 2
2014-04-08
Pld Architecture For Flexible Placement Of Ip Function Blocks
App 20130214815 - Lee; Andy L. ;   et al.
2013-08-22
Pessimism removal in the modeling of simultaneous switching noise
Grant 8,443,321 - Fender , et al. May 14, 2
2013-05-14
PLD architecture for flexible placement of IP function blocks
Grant 8,407,649 - Lee , et al. March 26, 2
2013-03-26
Pld Architecture For Flexible Placement Of Ip Function Blocks
App 20120217998 - Lee; Andy L. ;   et al.
2012-08-30
PLD architecture for flexible placement of IP function blocks
Grant 8,201,129 - Lee , et al. June 12, 2
2012-06-12
Redundancy structures and methods in a programmable logic device
Grant 8,191,025 - Chan , et al. May 29, 2
2012-05-29
Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices
App 20120089958 - Lewis; David ;   et al.
2012-04-12
Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage
Grant 8,103,975 - Lewis , et al. January 24, 2
2012-01-24
Power-driven timing analysis and placement for programmable logic
Grant 8,099,692 - Kretchmer , et al. January 17, 2
2012-01-17
Simultaneous switching noise analysis using superposition techniques
Grant 7,983,880 - Fender , et al. July 19, 2
2011-07-19
Power-driven timing analysis and placement for programmable logic
Grant 7,861,190 - Kretchmer , et al. December 28, 2
2010-12-28
Versatile logic element and logic array block
Grant 7,671,626 - Lewis , et al. March 2, 2
2010-03-02
Distributed memory in field-programmable gate array integrated circuit devices
Grant 7,656,191 - Lewis , et al. February 2, 2
2010-02-02
Redundancy structures and methods in a programmable logic device
Grant 7,644,386 - Chan , et al. January 5, 2
2010-01-05
Pld Architecture For Flexible Placement Of Ip Function Blocks
App 20090224800 - Lee; Andy L. ;   et al.
2009-09-10
PLD architecture for flexible placement of IP function blocks
Grant 7,584,447 - Lee , et al. September 1, 2
2009-09-01
Apparatus And Methods For Optimizing The Performance Of Programmable Logic Devices
App 20080263490 - Lewis; David ;   et al.
2008-10-23
Versatile logic element and logic array block
Grant 7,432,734 - Lewis , et al. October 7, 2
2008-10-07
Distributed memory in field-programmable gate array integrated circuit devices
App 20080231316 - Lewis; David ;   et al.
2008-09-25
Apparatus and methods for optimizing the performance of programmable logic devices
Grant 7,400,167 - Lewis , et al. July 15, 2
2008-07-15
Distributed memory in field-programmable gate array integrated circuit devices
Grant 7,391,236 - Lewis , et al. June 24, 2
2008-06-24
Distributed random access memory in a programmable logic device
Grant 7,304,499 - Lewis , et al. December 4, 2
2007-12-04
Versatile Logic Element And Logic Array Block
App 20070252617 - Lewis; David M. ;   et al.
2007-11-01
Multiplexing device including a hardwired multiplexer in a programmable logic device
Grant 7,253,660 - Leventis , et al. August 7, 2
2007-08-07
Distributed memory in field-programmable gate array integrated circuit devices
App 20070146178 - Lewis; David ;   et al.
2007-06-28
Data compression and decompression techniques for programmable circuits
Grant 7,236,633 - Lewis , et al. June 26, 2
2007-06-26
Versatile logic element and logic array block
Grant 7,218,133 - Lewis , et al. May 15, 2
2007-05-15
Method and apparatus for enhancing signal routability
Grant 7,185,306 - Leventis , et al. February 27, 2
2007-02-27
Apparatus and methods for optimizing the performance of programmable logic devices
App 20070040577 - Lewis; David ;   et al.
2007-02-22
Redundancy structures and methods in a programmable logic device
Grant 7,180,324 - Chan , et al. February 20, 2
2007-02-20
Routing architecture with high speed I/O bypass path
Grant 7,132,852 - Vest , et al. November 7, 2
2006-11-07
Flexible routing resources in a programmable logic device
Grant 7,098,687 - Leventis , et al. August 29, 2
2006-08-29
Distributed random access memory in a programmable logic device
Grant 7,084,665 - Lewis , et al. August 1, 2
2006-08-01
Methods for designing PLD architectures for flexible placement of IP function blocks
Grant 7,058,920 - Lee , et al. June 6, 2
2006-06-06
PLD architecture for flexible placement of IP functions blocks
App 20060033527 - Lee; Andy L. ;   et al.
2006-02-16
Redundancy structures and methods in a programmable logic device
App 20050264318 - Chan, Michael ;   et al.
2005-12-01
Routing architecture for a programmable logic device
Grant 6,970,014 - Lewis , et al. November 29, 2
2005-11-29
Programmable logic device with redundant circuitry
Grant 6,965,249 - Lane , et al. November 15, 2
2005-11-15
Routing architecture with high speed I/O bypass path
App 20050231236 - Vest, William Bradley ;   et al.
2005-10-20
Versatile logic element and logic array block
Grant 6,937,064 - Lewis , et al. August 30, 2
2005-08-30
Versatile logic element and logic array block
App 20050127944 - Lewis, David M. ;   et al.
2005-06-16
System and method for optimizing routing lines in a programmable logic device
Grant 6,895,570 - Lewis , et al. May 17, 2
2005-05-17
Use of dangling partial lines for interfacing in a PLD
Grant 6,859,065 - Johnson , et al. February 22, 2
2005-02-22
Flexible I/O routing resources
Grant 6,826,741 - Johnson , et al. November 30, 2
2004-11-30
Use of dangling partial lines for interfacing in a PLD
App 20040108871 - Johnson, Brian D. ;   et al.
2004-06-10
PLD architecture for flexible placement of IP function blocks
App 20030237071 - Lee, Andy L. ;   et al.
2003-12-25
Use of dangling partial lines for interfacing in a PLD
Grant 6,653,862 - Johnson , et al. November 25, 2
2003-11-25
Routing architecture for a programmable logic device
Grant 6,630,842 - Lewis , et al. October 7, 2
2003-10-07
PLD architecture for flexible placement of IP function blocks
Grant 6,605,962 - Lee , et al. August 12, 2
2003-08-12
Programmable logic device with redundant circuitry
App 20030072185 - Lane, Christopher ;   et al.
2003-04-17
Use of dangling partial lines for interfacing in a PLD
App 20020163358 - Johnson, Brian D. ;   et al.
2002-11-07
System and method for asymmetric routing lines
App 20020166106 - Lewis, David M. ;   et al.
2002-11-07
PLD architecture for flexible placement of IP function blocks
App 20020163356 - Lee, Andy L. ;   et al.
2002-11-07

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