Letavic; Theodore

Patent Applications and Registrations

Patent applications and USPTO patent grants for Letavic; Theodore.The latest application filed is for "complementary asymmetric high voltage devices and method of fabrication".

Company Profile

1.15.8

Letavic; Theodore - Putnam Valley NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Bragg gratings with airgap cladding Grant 10,795,082 - Jacob , et al. October 6, 2	2020-10-06
Semiconductor device structure with a tapered field plate and cylindrical drift region geometry Grant 7,989,881 - Letavic , et al. August 2, 2	2011-08-02
High-voltage device structure Grant 7,968,938 - Letavic , et al. June 28, 2	2011-06-28
Prevention of parasitic channel in an integrated SOI process Grant 7,544,998 - Letavic June 9, 2	2009-06-09
Dynamic control of capacitance elements in field effect structures Grant 7,485,916 - Petruzzello , et al. February 3, 2	2009-02-03
Complementary Asymmetric High Voltage Devices and Method of Fabrication App 20080308874 - Letavic; Theodore ; et al.	2008-12-18
Semiconductor Device Structure With a Tapered Field Plate and Cylindrical Drift Region Geometry App 20080272428 - Letavic; Theodore ; et al.	2008-11-06
Silicon-on-insulator device Grant 7,439,585 - Letavic , et al. October 21, 2	2008-10-21
High-Voltage Device Structure App 20080128743 - Letavic; Theodore ; et al.	2008-06-05
Dynamic control of capacitance elements in field effect structures App 20070080389 - Petruzzello; John ; et al.	2007-04-12
Silicon-on-insulator photodiode optical monitoring system for color temperature control in solid state light systems App 20070034899 - Petruzzello; John ; et al.	2007-02-15
Silicon-on-insulator device App 20060163654 - Letavic; Theodore ; et al.	2006-07-27
Prevention of parasitic channel in an integrated soi process App 20060145256 - Letavic; Theodore	2006-07-06
SOI-LDMOS device with integral voltage sense electrodes Grant 6,833,726 - Petruzzello , et al. December 21, 2	2004-12-21
SOI-LDMOS device with integral voltage sense electrodes App 20040164351 - Petruzzello, John ; et al.	2004-08-26
SOI-LDMOS device with integral voltage sense electrodes Grant 6,717,214 - Pettruzello , et al. April 6, 2	2004-04-06
Lateral insulated gate bipolar PMOS device Grant 6,661,059 - Letavic , et al. December 9, 2	2003-12-09
Lateral thin-film silicon-on-insulator (SOI) device having a lateral drift region with a retrograde doping profile, and method of making such a device Grant 6,313,489 - Letavic , et al. November 6, 2	2001-11-06
High voltage thin film transistor with improved on-state characteristics and method for making same Grant 6,310,378 - Letavic , et al. October 30, 2	2001-10-30
Lateral thin-film silicon-on-insulator (SOI) PMOS device having a drain extension region Grant 6,127,703 - Letavic , et al. October 3, 2	2000-10-03
Lateral thin-film Silicon-On-Insulator (SOI) device having multiple zones in the drift region Grant 6,023,090 - Letavic , et al. February 8, 2	2000-02-08
Lateral thin-film silicon-on-insulator (SOI) JFET device Grant 5,973,341 - Letavic , et al. October 26, 1	1999-10-26
Lateral thin-film SOI devices with graded top oxide and graded drift region Grant 5,969,387 - Letavic , et al. October 19, 1	1999-10-19

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