loadpatents
name:-0.013638973236084
name:-0.026236057281494
name:-0.00058984756469727
Lester; Robert Allan Patent Filings

Lester; Robert Allan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lester; Robert Allan.The latest application filed is for "independent power collapse methodology".

Company Profile
0.21.9
  • Lester; Robert Allan - Round Rock TX
  • Lester; Robert Allan - Tomball TX
  • Lester; Robert Allan - Houston TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Independent power collapse methodology
Grant 9,785,211 - Koob , et al. October 10, 2
2017-10-10
Independent power collapse methodology
App 20160239060 - Koob; Christopher Edward ;   et al.
2016-08-18
System and method for generating and using predicates within a single instruction packet
Grant 8,990,543 - Codrescu , et al. March 24, 2
2015-03-24
Buffer management structure with selective flush
Grant 8,117,420 - Shen , et al. February 14, 2
2012-02-14
Multi-mode instruction memory unit
Grant 7,685,411 - Ahmed , et al. March 23, 2
2010-03-23
Buffer Management Structure with Selective Flush
App 20100037028 - Shen; Jian ;   et al.
2010-02-11
System and Method of Selectively Committing a Result of an Executed Instruction
App 20090235051 - Codrescu; Lucian ;   et al.
2009-09-17
Transaction generator for initialization, rebuild, and verify of memory
Grant 7,155,568 - Richard , et al. December 26, 2
2006-12-26
Instruction memory unit and method of operation
App 20060230259 - Ahmed; Muhammad ;   et al.
2006-10-12
Removable memory cartridge system for use with a server or other processor-based device
Grant 7,116,241 - Post , et al. October 3, 2
2006-10-03
Removable memory cartridge system for use with a server or other processor-based device
Grant 6,975,241 - Post , et al. December 13, 2
2005-12-13
Removable memory cartridge system for use with a server or other processor-based device
Grant 6,747,563 - Post , et al. June 8, 2
2004-06-08
Removable memory cartridge system for use with a server or other processor-based device
App 20030201902 - Post, Christian H. ;   et al.
2003-10-30
Removable memory cartridge system for use with a server or other processor-based device
App 20030193403 - Post, Christian H. ;   et al.
2003-10-16
Removable memory cartridge system for use with a server or other processor-based device
App 20030193402 - Post, Christian H. ;   et al.
2003-10-16
Removable memory cartridge system for use with a server or other processor-based device
Grant 6,608,564 - Post , et al. August 19, 2
2003-08-19
Transaction generator for initialization, rebuild, and verify of memory
App 20030079073 - Richard, Elizabeth Anne ;   et al.
2003-04-24
System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops
Grant 6,470,429 - Jones , et al. October 22, 2
2002-10-22
System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system
Grant 6,363,439 - Battles , et al. March 26, 2
2002-03-26
Removable memory cartridge system for use with a server or other processor-based device
App 20020010835 - Post, Christian H. ;   et al.
2002-01-24
Accelerated graphics port programmable memory access arbiter
Grant 6,078,338 - Horan , et al. June 20, 2
2000-06-20
Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device
Grant 5,999,198 - Horan , et al. December 7, 1
1999-12-07
Generating an error signal when accessing an invalid memory page
Grant 5,990,914 - Horan , et al. November 23, 1
1999-11-23
Accelerated graphics port multiple entry gart cache allocation system and method
Grant 5,949,436 - Horan , et al. September 7, 1
1999-09-07
Accelerated graphics port memory mapped status and control registers
Grant 5,936,640 - Horan , et al. August 10, 1
1999-08-10
Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus
Grant 5,923,859 - Melo , et al. July 13, 1
1999-07-13
Valid flag for disabling allocation of accelerated graphics port memory space
Grant 5,914,727 - Horan , et al. June 22, 1
1999-06-22
Accelerated Graphics Port two level Gart cache having distributed first level caches
Grant 5,905,509 - Jones , et al. May 18, 1
1999-05-18
Direct memory access controller having programmable timing
Grant 5,884,095 - Wolford , et al. March 16, 1
1999-03-16

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