loadpatents
Patent applications and USPTO patent grants for Leitz; Christopher W..The latest application filed is for "semiconductor structures with structural homogeneity".
Patent | Date |
---|---|
Structure and method for a high-speed semiconductor device having a Ge channel layer Grant 8,436,336 - Lee , et al. May 7, 2 | 2013-05-07 |
Methods of fabricating semiconductor devices having strained dual channel layers Grant 7,566,606 - Currie , et al. July 28, 2 | 2009-07-28 |
Semiconductor Structures With Structural Homogeneity App 20080135830 - Westhoff; Richard ;   et al. | 2008-06-12 |
STRUCTURE AND METHOD FOR A HIGH-SPEED SEMICONDUCTOR DEVICE HAVING A Ge CHANNEL LAYER App 20080128747 - Lee; Minjoo L. ;   et al. | 2008-06-05 |
Methods for Selective Placement of Dislocation Arrays App 20080070397 - Lochtefeld; Anthony J. ;   et al. | 2008-03-20 |
Semiconductor structures with structural homogeneity Grant 7,332,417 - Westhoff , et al. February 19, 2 | 2008-02-19 |
Structure and method for a high-speed semiconductor device having a Ge channel layer Grant 7,301,180 - Lee , et al. November 27, 2 | 2007-11-27 |
Structures with planar strained layers App 20070072354 - Lee; Minjoo L. ;   et al. | 2007-03-29 |
Semiconductor devices having strained dual channel layers App 20070032009 - Currie; Matthew T. ;   et al. | 2007-02-08 |
Structures with planar strained layers Grant 7,141,820 - Lee , et al. November 28, 2 | 2006-11-28 |
Semiconductor devices having strained dual channel layers Grant 7,138,310 - Currie , et al. November 21, 2 | 2006-11-21 |
Enhancement of p-type metal-oxide-semiconductor field effect transistors App 20050151164 - Leitz, Christopher W. ;   et al. | 2005-07-14 |
Enhancement of P-type metal-oxide-semiconductor field effect transistors Grant 6,916,727 - Leitz , et al. July 12, 2 | 2005-07-12 |
Semiconductor structures with structural homogeneity App 20040214407 - Westhoff, Richard ;   et al. | 2004-10-28 |
Structures with planar strained layers App 20040164318 - Lee, Minjoo L. ;   et al. | 2004-08-26 |
Selective placement of dislocation arrays App 20040115916 - Lochtefeld, Anthony J. ;   et al. | 2004-06-17 |
Formation of planar strained layers Grant 6,730,551 - Lee , et al. May 4, 2 | 2004-05-04 |
Semiconductor devices having strained dual channel layers App 20040026765 - Currie, Matthew T. ;   et al. | 2004-02-12 |
Structure and method for a high-speed semiconductor device App 20030052334 - Lee, Minjoo L. ;   et al. | 2003-03-20 |
Formation of planar strained layers App 20030025131 - Lee, Minjoo L. ;   et al. | 2003-02-06 |
Enhancement of p-type metal-oxide-semiconductor field effect transistors App 20020197803 - Leitz, Christopher W. ;   et al. | 2002-12-26 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.