Lei; Shuen-Cheng
Patent Applications and Registrations
Patent applications and USPTO patent grants for Lei; Shuen-Cheng.The latest application filed is for "method for predicting tolerable spacing between conductors in semiconductor process".
- Lei; Shuen-Cheng - Taipei County N/A TW
- Lei; Shuen-Cheng - Tainan County TW
| Patent | Date |
|---|---|
| Method for predicting tolerable spacing between conductors in semiconductor process Grant 8,516,400 - Kuo , et al. August 20, 2 | 2013-08-20 |
| Method and pattern carrier for optimizing inspection recipe of defect inspection tool Grant 8,487,644 - Huang , et al. July 16, 2 | 2013-07-16 |
| Method For Predicting Tolerable Spacing Between Conductors In Semiconductor Process App 20120112782 - Kuo; Chien-Li ; et al. | 2012-05-10 |
| Method And Pattern Carrier For Optimizing Inspection Recipe Of Defect Inspection Tool App 20120019279 - Huang; Pong-Wey ; et al. | 2012-01-26 |
| Alignment Mark App 20100327451 - Chou; Ling-Chun ; et al. | 2010-12-30 |
| Inspection Structure And Method For In-line Monitoring Wafer App 20100308220 - Chou; Ling-Chun ; et al. | 2010-12-09 |
| Alignment mark and defect inspection method Grant 7,817,265 - Chou , et al. October 19, 2 | 2010-10-19 |
| Alignment Mark And Defect Inspection Method App 20100073671 - Chou; Ling-Chun ; et al. | 2010-03-25 |
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