loadpatents
name:-0.0076279640197754
name:-0.008012056350708
name:-0.0017201900482178
Lei; Cheok-Kei Patent Filings

Lei; Cheok-Kei

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lei; Cheok-Kei.The latest application filed is for "metal cut optimization for standard cells".

Company Profile
9.15.19
  • Lei; Cheok-Kei - Macau MO
  • Lei; Cheok-Kei - Hsinchu TW
  • LEI; CHEOK-KEI - ANDAR AC MO
  • Lei; Cheok-Kei - Andar AC Macau TW
  • Lei; Cheok-Kei - Andar MO
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Multiplexer
Grant 11,392,743 - Liu , et al. July 19, 2
2022-07-19
Metal Cut Optimization For Standard Cells
App 20210271794 - Lei; Cheok-Kei ;   et al.
2021-09-02
System and Method for Transistor Placement in Standard Cell Layout
App 20210200927 - Lei; Cheok-Kei ;   et al.
2021-07-01
Capacitive Isolation Structure Insert For Reversed Signals
App 20210192118 - LEI; Cheok-Kei ;   et al.
2021-06-24
Metal cut optimization for standard cells
Grant 11,030,368 - Lei , et al. June 8, 2
2021-06-08
Capacitive isolation structure insert for reversed signals
Grant 10,943,050 - Lei , et al. March 9, 2
2021-03-09
Multiplexer
App 20200395938 - Liu; Chi-Lin ;   et al.
2020-12-17
Layout For Integrated Circuit And The Integrated Circuit
App 20200285797 - LEI; CHEOK-KEI ;   et al.
2020-09-10
Metal Cut Optimization For Standard Cells
App 20200285792 - LEI; Cheok-Kei ;   et al.
2020-09-10
Metal cut optimization for standard cells
Grant 10,691,849 - Lei , et al.
2020-06-23
Layout for integrated circuit and the integrated circuit
Grant 10,685,162 - Lei , et al.
2020-06-16
Capacitive Isolation Structure Insert For Reversed Signals
App 20200134130 - LEI; Cheok-Kei ;   et al.
2020-04-30
Layout For Integrated Circuit And The Integrated Circuit
App 20190121931 - LEI; CHEOK-KEI ;   et al.
2019-04-25
Metal Cut Optimization for Standard Cells
App 20190095552 - LEI; Cheok-Kei ;   et al.
2019-03-28
Layout method for integrated circuit and layout of the integrated circuit
Grant 10,163,883 - Lei , et al. Dec
2018-12-25
Layout Method For Integrated Circuit And Layout Of The Integrated Circuit
App 20170365592 - LEI; CHEOK-KEI ;   et al.
2017-12-21
Performance-driven and gradient-aware dummy insertion for gradient-sensitive array
Grant 9,659,920 - Huang , et al. May 23, 2
2017-05-23
Performance-driven And Gradient-aware Dummy Insertion For Gradient-sensitive Array
App 20150179627 - Huang; Mu-Jen ;   et al.
2015-06-25
Performance-driven and gradient-aware dummy insertion for gradient-sensitive array
Grant 8,978,000 - Huang , et al. March 10, 2
2015-03-10
System and methods for converting planar design to FinFET design
Grant 8,875,076 - Lin , et al. October 28, 2
2014-10-28
System And Methods For Converting Planar Design To Finfet Design
App 20140215420 - LIN; Yi-Tang ;   et al.
2014-07-31
Automatic flow of megacell generation
Grant 8,789,004 - Chen , et al. July 22, 2
2014-07-22
Performance-driven And Gradient-aware Dummy Insertion For Gradient-sensitive Array
App 20140189625 - Huang; Mu-Jen ;   et al.
2014-07-03
System and methods for converting planar design to FinFET design
Grant 8,726,220 - Lin , et al. May 13, 2
2014-05-13
System and methods for converting planar design to FinFET design
Grant 8,621,406 - Lei , et al. December 31, 2
2013-12-31
Automatic Flow Of Megacell Generation
App 20130091483 - CHEN; Hsiao-Hui ;   et al.
2013-04-11
System And Method For Hierarchy Reconstruction From Flattened Graphic Database System Layout
App 20130019219 - Chen; Shu-Yu ;   et al.
2013-01-17
System And Methods For Converting Planar Design To Finfet Design
App 20120278777 - LIN; Yi-Tang ;   et al.
2012-11-01
System And Methods For Converting Planar Design To Finfet Design
App 20120278776 - LEI; Cheok-Kei ;   et al.
2012-11-01

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