Leenstra; Jens

Patent Applications and Registrations

Patent applications and USPTO patent grants for Leenstra; Jens.The latest application filed is for "instruction scheduling approach to improve processor performance".

Company Profile

0.39.36

Leenstra; Jens - Boeblingen DE
Leenstra; Jens - Bondorf DE
Leenstra; Jens - Bosdorf DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Instruction scheduling approach to improve processor performance Grant 9,256,430 - Koehl , et al. February 9, 2	2016-02-09
Mechanism to speed-up multithreaded execution by register file write port reallocation Grant 9,207,995 - Boersma , et al. December 8, 2	2015-12-08
Apparatus and method for calculating an SHA-2 hash function in a general purpose processor Grant 9,164,725 - Boersma , et al. October 20, 2	2015-10-20
Techniques for reusing components of a logical operations functional block as an error correction code correction unit Grant 9,043,673 - Kaltenback , et al. May 26, 2	2015-05-26
Instruction Scheduling Approach To Improve Processor Performance App 20150127926 - KOEHL; Juergen ; et al.	2015-05-07
Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency Grant 8,977,835 - Boersma , et al. March 10, 2	2015-03-10
Instruction scheduling approach to improve processor performance Grant 8,972,961 - Koehl , et al. March 3, 2	2015-03-03
Byte selection and steering logic for combined byte shift and byte permute vector unit Grant 8,959,275 - Kaltenbach , et al. February 17, 2	2015-02-17
Byte selection and steering logic for combined byte shift and byte permute vector unit Grant 8,959,276 - Kaltenbach , et al. February 17, 2	2015-02-17
Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latency Grant 8,949,575 - Boersma , et al. February 3, 2	2015-02-03
Instruction scheduling approach to improve processor performance Grant 8,935,685 - Koehl , et al. January 13, 2	2015-01-13
Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product Grant 8,903,882 - Boersma , et al. December 2, 2	2014-12-02
Fast predicate table scans using single instruction, multiple data architecture Grant 8,843,527 - Diner , et al. September 23, 2	2014-09-23
Fast predicate table scans using single instruction, multiple data architecture Grant 8,832,158 - Diner , et al. September 9, 2	2014-09-09
Byte Selection And Steering Logic For Combined Byte Shift And Byte Permute Vector Unit App 20140129809 - Kaltenbach; Markus ; et al.	2014-05-08
Byte Selection And Steering Logic For Combined Byte Shift And Byte Permute Vector Unit App 20140101358 - Kaltenbach; Markus ; et al.	2014-04-10
Reducing Issue-to-issue Latency By Reversing Processing Order In Half-pumped Simd Execution Units App 20140075153 - Boersma; Maarten J. ; et al.	2014-03-13
Fast Predicate Table Scans Using Single Instruction, Multiple Data Architecture App 20130262370 - Diner; Eduard ; et al.	2013-10-03
Fast Predicate Table Scans Using Single Instruction, Multiple Data Architecture App 20130262519 - Diner; Eduard ; et al.	2013-10-03
Techniques for Reusing Components of a Logical Operations Functional Block as an Error Correction Code Correction Unit App 20130227375 - Kaltenback; Markus ; et al.	2013-08-29
Reducing Issue-to-issue Latency By Reversing Processing Order In Half-pumped Simd Execution Units App 20130159666 - Boersma; Maarten J. ; et al.	2013-06-20
Permute unit and method to operate a permute unit Grant 8,312,069 - Gemmeke , et al. November 13, 2	2012-11-13
Instruction Scheduling Approach To Improve Processor Performance App 20120216016 - Koehl; Juergen ; et al.	2012-08-23
Method And Data Processing Unit For Calculating At Least One Multiply-sum Of Two Carry-less Multiplications Of Two Input Operands, Data Processing Program And Computer Program Product App 20120150933 - Boersma; Maarten J. ; et al.	2012-06-14
Apparatus And Method For Calculating An Sha-2 Hash Function In A General Purpose Processor App 20120128149 - Boersma; Maarten J. ; et al.	2012-05-24
Mechanism To Speed-up Multithreaded Execution By Register File Write Port Reallocation App 20120110271 - Boersma; Maarten J. ; et al.	2012-05-03
Instruction Scheduling Approach To Improve Processor Performance App 20110289297 - Koehl; Juergen ; et al.	2011-11-24
Method to reduce power consumption of a register file with multi SMT support Grant 8,046,566 - Abernathy , et al. October 25, 2	2011-10-25
Method of operand width reduction to enable usage of narrower saturation adder Grant 7,962,538 - Gemmeke , et al. June 14, 2	2011-06-14
System and method for scanning sequential logic elements Grant 7,913,132 - Gemmeke , et al. March 22, 2	2011-03-22
Method and system for verifying the equivalence of digital circuits Grant 7,890,901 - Gemmeke , et al. February 15, 2	2011-02-15
Method and system for pipeline reduction Grant 7,844,799 - Leenstra , et al. November 30, 2	2010-11-30
Electronic circuit for implementing a permutation operation Grant 7,783,690 - Leenstra , et al. August 24, 2	2010-08-24
Method and apparatus for register renaming Grant 7,769,986 - Abernathy , et al. August 3, 2	2010-08-03
Design structure to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit Grant 7,735,038 - Gemmeke , et al. June 8, 2	2010-06-08
Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit Grant 7,639,046 - Gemmeke , et al. December 29, 2	2009-12-29
Method to Reduce Power Consumption of a Register File with Multi SMT Support App 20090292892 - Abernathy; Christopher M. ; et al.	2009-11-26
System and Method for Scanning Sequential Logic Elements App 20090135961 - Gemmeke; Tobias ; et al.	2009-05-28
Reducing register file leakage current within a processor Grant 7,509,511 - Barowski , et al. March 24, 2	2009-03-24
Systems and methods for adaptively mapping an instruction cache Grant 7,469,332 - Basso , et al. December 23, 2	2008-12-23
Method And Apparatus For Register Renaming App 20080276076 - Abernathy; Christopher Michael ; et al.	2008-11-06
Design Structure To Reduce Power Consumption Within A Clock Gated Synchronous Circuit And Clock Gated Synchronous Circuit App 20080169842 - Gemmeke; Tobias ; et al.	2008-07-17
Method To Reduce Power Consumption Within A Clock Gated Synchronous Circuit And Clock Gated Synchronous Circuit App 20080169841 - Gemmeke; Tobias ; et al.	2008-07-17
Permute Unit and Method to Operate a Permute Unit App 20080130871 - Gemmeke; Tobias ; et al.	2008-06-05
Method And System For Verifying The Equivalence Of Digital Circuits App 20070226664 - Gemmeke; Tobias ; et al.	2007-09-27
Method Of Operand Width Reduction To Enable Usage Of Narrower Saturation Adder App 20070180016 - Gemmeke; Tobias ; et al.	2007-08-02
Circuit Arrangement and Method to Reduce Leakage Power and to Increase the Performance of a Circuit App 20070165343 - Barowski; Harry ; et al.	2007-07-19
Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture Grant 7,228,403 - Leber , et al. June 5, 2	2007-06-05
Electronic circuit for implementing a permutation operation App 20070011220 - Leenstra; Jens ; et al.	2007-01-11
Systems and methods for adaptively mapping an instruction cache App 20060200615 - Basso; Claude ; et al.	2006-09-07
Device and method for decoding an address word into word-line signals Grant 6,977,863 - Buettner , et al. December 20, 2	2005-12-20
Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environments Grant 6,918,119 - Haller , et al. July 12, 2	2005-07-12
Device and method for decoding an address word into word-line signals App 20050128845 - Buettner, Stefan ; et al.	2005-06-16
Device and method for decoding an address word into word-line signals Grant 6,873,567 - Buettner , et al. March 29, 2	2005-03-29
Rename finish conflict detection and recovery Grant 6,829,699 - Leenstra , et al. December 7, 2	2004-12-07
Read/write alignment scheme for port reduction of multi-port SRAM cells Grant 6,785,781 - Leenstra , et al. August 31, 2	2004-08-31
Hierarchical priority filter with integrated serialization for determining the entry with the highest priority in a buffer memory Grant 6,725,332 - Leenstra , et al. April 20, 2	2004-04-20
Device and method for decoding an address word into word-line signals App 20040027885 - Buettner, Stefan ; et al.	2004-02-12
Method and system for pipeline reduction App 20030208672 - Leenstra, Jens ; et al.	2003-11-06
Pre-committing instruction sequences App 20020152259 - Trong, Son Dao ; et al.	2002-10-17
Method for handling 32 bit results for an out-of-order processor with A 64 bit architecture App 20020129224 - Leber, Petra ; et al.	2002-09-12
Rename finish conflict detection and recovery App 20020083304 - Leenstra, Jens ; et al.	2002-06-27
Active window management for reorder buffer App 20010052055 - Haller, Wilhelm E. ; et al.	2001-12-13
Read/write alignment scheme for port red uction of multi-port SRAM cells App 20010034817 - Leenstra, Jens ; et al.	2001-10-25
Hierarchical priority filter with integrated serialization App 20010029557 - Leenstra, Jens ; et al.	2001-10-11
Embedding of dynamic circuits in a static environment App 20010026172 - Leenstra, Jens ; et al.	2001-10-04

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