| Patent | Date |
|---|
Iap Inhibitors
App 20110288116 - Condon; Stephen M. ; et al. | 2011-11-24 |
Key-hole free process for high aspect ratio gap filling with reentrant spacer
Grant 7,482,278 - Ying , et al. January 27, 2 | 2009-01-27 |
Laminated silicate glass layer etch stop method for fabricating microelectronic product
Grant 7,160,811 - Chen , et al. January 9, 2 | 2007-01-09 |
Method for manufacturing dual damascene structure with a trench formed first
App 20060194426 - Yang; Chin-Tien ; et al. | 2006-08-31 |
Method for manufacturing dual damascene structure with a trench formed first
Grant 7,056,821 - Yang , et al. June 6, 2 | 2006-06-06 |
Bond pad scheme for Cu process
Grant 7,015,129 - Lai , et al. March 21, 2 | 2006-03-21 |
Method for manufacturing dual damascene structure with a trench formed first
App 20060040498 - Yang; Chin-Tien ; et al. | 2006-02-23 |
Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing
Grant 6,956,254 - Yang , et al. October 18, 2 | 2005-10-18 |
Interconnect structure and method for its fabricating
App 20050173799 - Jou, Juan-Jann ; et al. | 2005-08-11 |
Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing
App 20050116281 - Yang, Chin-Tien ; et al. | 2005-06-02 |
Bond pad scheme for Cu process
App 20050095836 - Lai, Chia-Hung ; et al. | 2005-05-05 |
Bond pad scheme for Cu process
Grant 6,844,626 - Lai , et al. January 18, 2 | 2005-01-18 |
Bond Pad Scheme For Cu Process
App 20040235223 - Lai, Chia-Hung ; et al. | 2004-11-25 |
Laminated silicate glass layer etch stop method for fabricating microelectronic product
App 20040074872 - Chen, Yen-Ming ; et al. | 2004-04-22 |
Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule
Grant 6,600,228 - Lee , et al. July 29, 2 | 2003-07-29 |
Process for making embedded DRAM circuits having capacitor under bit-line (CUB)
Grant 6,436,763 - Huang , et al. August 20, 2 | 2002-08-20 |
Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids
App 20020094644 - Chiang, Ming-Hsiung ; et al. | 2002-07-18 |
Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM)
Grant 6,403,416 - Huang , et al. June 11, 2 | 2002-06-11 |
Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule and device manufactured thereby
App 20020004310 - Lee, Yu-Hua ; et al. | 2002-01-10 |
Borderless dual damascene contact
Grant 6,323,118 - Shih , et al. November 27, 2 | 2001-11-27 |
Method for making a fuse structure for improved repaired yields on semiconductor memory devices
Grant 6,307,213 - Huang , et al. October 23, 2 | 2001-10-23 |
Simple Photo development step to form tisix gate in DRAM process
App 20010018165 - Lee, Yu-Hua | 2001-08-30 |
Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure
Grant 6,274,426 - Lee , et al. August 14, 2 | 2001-08-14 |
Process for forming a crown shaped capacitor structure for a DRAM device
Grant 6,235,580 - Lee , et al. May 22, 2 | 2001-05-22 |
Method to evaluate hemisperical grain (HSG) polysilicon surface
Grant 6,194,234 - Huang , et al. February 27, 2 | 2001-02-27 |
Node process integration technology to improve data retention for logic based embedded dram
Grant 6,187,659 - Ying , et al. February 13, 2 | 2001-02-13 |
Process to fabricate a cylindrical, capacitor structure under a bit line structure for a dynamic random access memory cell
Grant 6,165,839 - Lee , et al. December 26, 2 | 2000-12-26 |
Method for forming a fuse in integrated circuit application
Grant 6,162,686 - Huang , et al. December 19, 2 | 2000-12-19 |
Method for making a fuse structure for improved repaired yields on semiconductor memory devices
Grant 6,121,073 - Huang , et al. September 19, 2 | 2000-09-19 |
Inter-level dielectric planarization approach for a DRAM crown capacitor process
Grant 6,077,738 - Lee , et al. June 20, 2 | 2000-06-20 |
Robust dual damascene process
Grant 6,042,999 - Lin , et al. March 28, 2 | 2000-03-28 |
Keyhole-free process for high aspect ratio gap filing
Grant 6,033,981 - Lee , et al. March 7, 2 | 2000-03-07 |
Process to form a crown capacitor structure for a dynamic random access memory cell
Grant 6,015,733 - Lee , et al. January 18, 2 | 2000-01-18 |
Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings
Grant 5,985,765 - Hsiao , et al. November 16, 1 | 1999-11-16 |
Robust method of forming a cylinder capacitor for DRAM circuits
Grant 5,854,119 - Wu , et al. December 29, 1 | 1998-12-29 |
Method of forming a dram cell having a ring-type stacked capacitor
Grant 5,429,979 - Lee , et al. July 4, 1 | 1995-07-04 |
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