Lee; Yong Meng

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lee; Yong Meng.The latest application filed is for "structure and method for testing of pic with an upturned mirror".

Company Profile

0.35.40

Lee; Yong Meng - San Jose CA
Lee; Yong Meng - Mechanicville NY
Lee; Yong Meng - Singapore N/A SG
Lee; Yong-Meng - Hopewell Junction NY US
Lee; Yong Meng - Woodlands SG
Lee; Yong Meng - US
Lee; Yong Meng - Beacon NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Structure And Method For Testing Of Pic With An Upturned Mirror App 20210356518 - Soldano; Lucas ; et al.	2021-11-18
Structure And Method For Testing Of Pic With An Upturned Mirror App 20210356519 - Soldano; Lucas ; et al.	2021-11-18
Forming self-aligned NiSi placement with improved performance and yield Grant 9,607,989 - Wu , et al. March 28, 2	2017-03-28
Method for creating self-aligned SDB for minimum gate-junction pitch and epitaxy formation in a fin-type IC device Grant 9,524,911 - Tsai , et al. December 20, 2	2016-12-20
FORMING SELF-ALIGNED NiSi PLACEMENT WITH IMPROVED PERFORMANCE AND YIELD App 20160163702 - WU; Xusheng ; et al.	2016-06-09
Semiconductor Gate With Wide Top Or Bottom App 20160049488 - SHEN; Yan Ping ; et al.	2016-02-18
Depositing an etch stop layer before a dummy cap layer to improve gate performance Grant 9,209,258 - Zhou , et al. December 8, 2	2015-12-08
Forming a gate by depositing a thin barrier layer on a titanium nitride cap Grant 9,202,697 - Luo , et al. December 1, 2	2015-12-01
Using sacrificial oxide layer for gate length tuning and resulting device Grant 9,147,572 - Jha , et al. September 29, 2	2015-09-29
Depositing An Etch Stop Layer Before A Dummy Cap Layer To Improve Gate Performance App 20150249136 - ZHOU; Feng ; et al.	2015-09-03
Integrated circuits and methods of forming integrated circuits with interlayer dielectric protection Grant 9,123,783 - Wang , et al. September 1, 2	2015-09-01
Systems And Methods For Fabricating Gate Structures For Semiconductor Devices App 20150024585 - LUO; Tien-Ying ; et al.	2015-01-22
Using Sacrificial Oxide Layer For Gate Length Tuning And Resulting Device App 20140339612 - JHA; Ashish Kumar ; et al.	2014-11-20
Spacer Divot Sealing Method And Semiconductor Device Incorporating Same App 20140175562 - Wang; Haiting ; et al.	2014-06-26
Doped Flowable Pre-metal Dielectric App 20140151760 - WANG; Haiting ; et al.	2014-06-05
Integrated Circuits And Methods Of Forming Integrated Circuits With Interlayer Dielectric Protection App 20140131881 - Wang; Xin ; et al.	2014-05-15
Capacitor top plate over source/drain to form a 1T memory device Grant 8,716,081 - Teo , et al. May 6, 2	2014-05-06
Spacer protection and electrical connection for array device Grant 8,623,714 - Park , et al. January 7, 2	2014-01-07
Spacer-less low-K dielectric processes Grant 8,624,329 - Lee , et al. January 7, 2	2014-01-07
High-k Seal for Protection of Replacement Gates App 20140004677 - Li; Ying ; et al.	2014-01-02
Hybrid orientation substrate with stress layer Grant 8,274,115 - Teo , et al. September 25, 2	2012-09-25
Balancing NFET and PFET performance using straining layers Grant 8,106,462 - Chen , et al. January 31, 2	2012-01-31
Method of manufacture of an integrated circuit system with self-aligned isolation structures Grant 8,053,327 - Mishra , et al. November 8, 2	2011-11-08
Spacer Protection And Electrical Connection For Array Device App 20110227136 - Park; Jae-Eun ; et al.	2011-09-22
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS Grant 7,999,325 - Teh , et al. August 16, 2	2011-08-16
Balancing Nfet And Pfet Performance Using Straining Layers App 20110169096 - Chen; Xiangdong ; et al.	2011-07-14
Method and apparatus for post silicide spacer removal Grant 7,977,185 - Greene , et al. July 12, 2	2011-07-12
Integrated circuit having a plurality of MOSFET devices Grant 7,932,178 - Teo , et al. April 26, 2	2011-04-26
Threshold voltage improvement employing fluorine implantation and adjustment oxide layer Grant 7,893,502 - Li , et al. February 22, 2	2011-02-22
Threshold Voltage Improvement Employing Fluorine Implantation And Adjustment Oxide Layer App 20100289088 - Li; Weipeng ; et al.	2010-11-18
Method of implanting a non-dopant atom into a semiconductor device Grant 7,737,009 - Lindsay , et al. June 15, 2	2010-06-15
Spacer-less Low-K Dielectric Processes App 20100059831 - Lee; Yong Meng ; et al.	2010-03-11
Method to enhance device performance with selective stress relief Grant 7,659,174 - Lee , et al. February 9, 2	2010-02-09
Integrated Circuit System Employing Single Mask Layer Technique For Well Formation App 20100009527 - Lee; Yong Meng ; et al.	2010-01-14
Spacer-less low-k dielectric processes Grant 7,615,427 - Lee , et al. November 10, 2	2009-11-10
Silicided polysilicon spacer for enhanced contact area Grant 7,598,572 - Dyer , et al. October 6, 2	2009-10-06
Hybrid Orientation Substrate With Stress Layer App 20090236663 - Teo; Lee Wee ; et al.	2009-09-24
Structure and Method of Producing Isolation with Non-Dopant Implantation App 20090042359 - Lindsay; Richard ; et al.	2009-02-12
Method To Remove Spacer After Salicidation To Enhance Contact Etch Stop Liner Stress On Mos App 20090026549 - TEH; Young Way ; et al.	2009-01-29
Semiconductor System Having Complementary Strained Channels App 20080315317 - Lai; Chung Woh ; et al.	2008-12-25
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS Grant 7,445,978 - Teh , et al. November 4, 2	2008-11-04
Capacitor Top Plate Over Source/drain To Form A 1t Memory Device App 20080224228 - Teo; Lee Wee ; et al.	2008-09-18
Integrated Circuit Having A Plurality Of Mosfet Devices App 20080157223 - Teo; Lee Wee ; et al.	2008-07-03
Post-silicide spacer removal Grant 7,393,746 - Dyer , et al. July 1, 2	2008-07-01
Integrated Circuit System With Isolation App 20080150074 - Mishra; Shailendra ; et al.	2008-06-26
Hot Carrier Degradation Reduction Using Ion Implantation Of Silicon Nitride Layer App 20080128834 - Yang; Haining ; et al.	2008-06-05
Silicided Polysilicon Spacer For Enhanced Contact Area App 20080102612 - Dyer; Thomas W. ; et al.	2008-05-01
Post-silicide spacer removal App 20080090370 - Dyer; Thomas W. ; et al.	2008-04-17
Method Of Fabricating Structure For Integrated Circuit Incorporating Hybrid Orientation Technology And Trench Isolation Regions App 20080048269 - Chen; Xiangdong ; et al.	2008-02-28
Method To Enhance Device Performance With Selective Stress Relief App 20080050868 - Lee; Yong Meng ; et al.	2008-02-28
Structure and method to implement dual stressor layers with improved silicide control App 20080026523 - Lee; Yong Meng ; et al.	2008-01-31
Method to enhance device performance with selective stress relief Grant 7,309,637 - Lee , et al. December 18, 2	2007-12-18
Spacer-less low-k dielectric processes App 20070281410 - Lee; Yong Meng ; et al.	2007-12-06
Composite stress spacer Grant 7,256,084 - Lim , et al. August 14, 2	2007-08-14
Method And Apparatus For Post Silicide Spacer Removal App 20070161244 - Greene; Brian J. ; et al.	2007-07-12
Method to enhance device performance with selective stress relief App 20070134870 - Lee; Yong Meng ; et al.	2007-06-14
Integrated Circuits Having Strained Channel Field Effect Transistors And Methods Of Making App 20070099360 - Lee; Yong Meng ; et al.	2007-05-03
Double-gated silicon-on-insulator (SOI) transistors with corner rounding Grant 7,141,854 - Lee , et al. November 28, 2	2006-11-28
Composite stress spacer App 20060252194 - Lim; Khee Yong ; et al.	2006-11-09
Method to remove spacer after salicidation to enhance contact etch stop liner stress on MOS App 20060249794 - Teh; Young Way ; et al.	2006-11-09
Hot Carrier Degradation Reduction Using Ion Implantation Of Silicon Nitride Layer App 20060151843 - Yang; Haining ; et al.	2006-07-13
Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding Grant 6,927,104 - Lee , et al. August 9, 2	2005-08-09
Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding App 20050059194 - Lee, Yong Meng ; et al.	2005-03-17
Method of forming double-gate semiconductor-on-insulator (SOI) transistors Grant 6,835,609 - Lee , et al. December 28, 2	2004-12-28
Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance Grant 6,787,404 - Lee , et al. September 7, 2	2004-09-07
Method for forming damascene dual gate for improved oxide uniformity and control Grant 6,583,011 - Xia , et al. June 24, 2	2003-06-24
Selective Salicide Process By Reformation Of Silicon Nitride Sidewall Spacers App 20020123192 - Lee, Yong Meng	2002-09-05
Selective formation of hydrogen rich PECVD silicon nitride for improved NMOS transistor performance Grant 6,372,569 - Lee , et al. April 16, 2	2002-04-16
Selective salicide process by reformation of silicon nitride sidewall spacers Grant 6,258,648 - Lee July 10, 2	2001-07-10
Silicon nitride--TEOS oxide, salicide blocking layer for deep sub-micron devices Grant 6,025,267 - Pey , et al. February 15, 2	2000-02-15

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