loadpatents
name:-0.001399040222168
name:-0.0138099193573
name:-0.00047516822814941
Lee; Raymond T. Patent Filings

Lee; Raymond T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lee; Raymond T..The latest application filed is for "minimizing transistor size in integrated circuits".

Company Profile
0.12.0
  • Lee; Raymond T. - Sunnyvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Minimizing transistor size in integrated circuits
Grant 7,026,691 - Sander , et al. April 11, 2
2006-04-11
Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers
Grant 6,479,350 - Ling , et al. November 12, 2
2002-11-12
Minimizing transistor size in integrated circuits
Grant 6,287,953 - Sander , et al. September 11, 2
2001-09-11
Nitride disposable spacer to reduce mask count in CMOS transistor formation
Grant 6,218,224 - Lukanc , et al. April 17, 2
2001-04-17
Minimizing transistor size in integrated circuits
Grant 6,146,954 - Klein , et al. November 14, 2
2000-11-14
Multipurpose cap layer dielectric
Grant 6,114,235 - Foote , et al. September 5, 2
2000-09-05
Nitride disposable spacer to reduce mask count in CMOS transistor formation
Grant 6,103,563 - Lukanc , et al. August 15, 2
2000-08-15
Forming local interconnects in integrated circuits
Grant 6,051,881 - Klein , et al. April 18, 2
2000-04-18
Method for self-aligning polysilicon gates with field isolation and the resultant structure
Grant 6,046,088 - Klein , et al. April 4, 2
2000-04-04
Landing pad technology doubled up as a local interconnect and borderless contact for deep sub-half micrometer IC application
Grant 5,674,781 - Huang , et al. October 7, 1
1997-10-07
Landing pad technology doubled up as local interconnect and borderless contact for deep sub-half micrometer IC application
Grant 5,654,589 - Huang , et al. August 5, 1
1997-08-05
Method for eliminating window mask process in the fabrication of a semiconductor wafer when chemical-mechanical polish planarization is used
Grant 5,627,110 - Lee , et al. May 6, 1
1997-05-06

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