LEE; Peter Wung

Patent Applications and Registrations

Patent applications and USPTO patent grants for LEE; Peter Wung.The latest application filed is for "hierarchical nand memory device capable of performing concurrent and pipeline operations".

Company Profile

4.87.87

LEE; Peter Wung - Saratoga CA US
- Saratoga CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Hierarchical Nand Memory Device Capable Of Performing Concurrent And Pipeline Operations App 20190018778 - LEE; Peter Wung	2019-01-17
Plural Distributed PBS with Both Voltage and Current Sensing SA for J-Page Hierarchical NAND Array's Concurrent Operations App 20170352424 - Lee; Peter Wung	2017-12-07
Self-timed SLC NAND pipeline and concurrent program without verification Grant 9,666,286 - Lee May 30, 2	2017-05-30
NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations Grant 9,659,636 - Lee May 23, 2	2017-05-23
2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify Grant 9,613,704 - Lee April 4, 2	2017-04-04
Partial/full array/block erase for 2D/3D hierarchical NAND Grant 9,595,319 - Lee March 14, 2	2017-03-14
NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous erase, erase-verify, program, program-verify, and read operations Grant 9,530,492 - Lee December 27, 2	2016-12-27
Multi-task concurrent/pipeline NAND operations on all planes Grant 9,524,773 - Lee December 20, 2	2016-12-20
Partial/full Array/block Erase For 2d/3d Hierarchical Nand App 20160314833 - Lee; Peter Wung	2016-10-27
VSL-based VT-compensation and analog program scheme for NAND array without CSL Grant 9,443,579 - Lee September 13, 2	2016-09-13
NAND array architecture for multiple simultaneous program and read Grant 9,443,578 - Lee September 13, 2	2016-09-13
NAND array architecture for multiple simutaneous program and read Grant 9,437,306 - Lee September 6, 2	2016-09-06
Novel Lv Nand-cam Search Scheme Using Existing Circuits With Least Overhead App 20160172037 - Lee; Peter Wung	2016-06-16
Novel Nand Array Architecture For Multiple Simutaneous Program And Read App 20160141024 - Lee; Peter Wung	2016-05-19
Novel Nand Array Architecture For Multiple Simutaneous Program And Read App 20160111162 - Lee; Peter Wung	2016-04-21
Multi-task Concurrent/pipeline Nand Operations On All Planes App 20160099047 - Lee; Peter Wung	2016-04-07
Self-timed Slc Nand Pipeline And Concurrent Program Without Verification App 20160093384 - Lee; Peter Wung	2016-03-31
Multi-task concurrent/pipeline NAND operations on all planes Grant 9,293,205 - Lee March 22, 2	2016-03-22
Nand Array Hiarchical Bl Structures For Multiple-wl And All-bl Simultaneous Erase, Erase-verify, Program, Program-verify, And Read Operations App 20160078928 - Lee; Peter Wung	2016-03-17
Vsl-based Vt-compensation And Analog Program Scheme For Nand Array Without Csl App 20160049192 - Lee; Peter Wung	2016-02-18
NAND array architecture for multiple simutaneous program and read Grant 9,263,137 - Lee February 16, 2	2016-02-16
YUKAI VSL-BASED Vt-COMPENSATION FOR NAND MEMORY App 20160027504 - Lee; Peter Wung	2016-01-28
NAND array hiarchical BL structures for multiple-WL and all-BL simultaneous erase, erase-verify, program, program-verify, and read operations Grant 9,230,677 - Lee January 5, 2	2016-01-05
Low disturbance, power-consumption, and latency in NAND read and program-verify operations Grant 9,183,940 - Lee November 10, 2	2015-11-10
Low-voltage fast-write PMOS NVSRAM cell Grant 9,177,644 - Tsao , et al. November 3, 2	2015-11-03
1T1b and 2T2b flash-based, data-oriented EEPROM design Grant 9,177,658 - Lee , et al. November 3, 2	2015-11-03
10T NVSRAM cell and cell operations Grant 9,177,645 - Tsao , et al. November 3, 2	2015-11-03
Non-boosting program inhibit scheme in NAND design Grant 9,171,627 - Lee , et al. October 27, 2	2015-10-27
Shielding 2-cycle half-page read and program schemes for advanced NAND flash design Grant 9,087,595 - Lee July 21, 2	2015-07-21
HYBRID NAND WITH ALL-BL m-PAGE OPERATION SCHEME App 20150179269 - Lee; Peter Wung	2015-06-25
Different types of memory integrated in one chip by using a novel protocol Grant 9,063,849 - Lee , et al. June 23, 2	2015-06-23
Low-voltage page buffer to be used in NVM design Grant 9,019,764 - Lee , et al. April 28, 2	2015-04-28
On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation Grant 9,001,583 - Lee , et al. April 7, 2	2015-04-07
NOR-based BCAM/TCAM cell and array with NAND scalability Grant 9,001,545 - Lee April 7, 2	2015-04-07
Nand Array Hiarchical Bl Structures For Multiple-wl And All-bl Simultaneous Erase, Erase-verify, Program, Program-verify, And Read Operations App 20150078080 - Lee; Peter Wung	2015-03-19
Multi-task Concurrent/pipeline Nand Operations On All Planes App 20150078086 - Lee; Peter Wung	2015-03-19
1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN App 20150071007 - Lee; Peter Wung ; et al.	2015-03-12
NVSRAM cells with voltage flash charger Grant 8,976,588 - Lee March 10, 2	2015-03-10
Pseudo-8T NVSRAM cell with a charge-follower Grant 8,971,113 - Lee March 3, 2	2015-03-03
Method and architecture for improving defect detectability, coupling area, and flexibility of NVSRAM cells and arrays Grant 8,964,470 - Lee February 24, 2	2015-02-24
EEPROM-based, data-oriented combo NVM design Grant 8,933,500 - Lee , et al. January 13, 2	2015-01-13
8T NVSRAM cell and cell operations Grant 8,929,136 - Lee , et al. January 6, 2	2015-01-06
Novel Nand Array Architecture For Multiple Simutaneous Program And Read App 20150003151 - Lee; Peter Wung	2015-01-01
1T1b and 2T2b flash-based, data-oriented EEPROM design Grant 8,923,049 - Lee , et al. December 30, 2	2014-12-30
1T1b and 2T2b flash-based, data-oriented EEPROM design Grant 08923049 -	2014-12-30
Flexible 2T-based fuzzy and certain matching arrays Grant 8,917,551 - Lee , et al. December 23, 2	2014-12-23
Nor-based Bcam/tcam Cell And Array With Nand Scalability App 20140347933 - Lee; Peter Wung	2014-11-27
Low Disturbance, Power-consumption, And Latency In Nand Read And Program-verify Operations App 20140347928 - Lee; Peter Wung	2014-11-27
Write bias condition for 2T-string NOR flash cell Grant 8,837,221 - Lee , et al. September 16, 2	2014-09-16
EEPROM-based, data-oriented combo NVM design Grant 8,809,148 - Lee , et al. August 19, 2	2014-08-19
High speed high density nand-based 2T-NOR flash memory design Grant 8,773,903 - Lee , et al. July 8, 2	2014-07-08
Pseudo-8t Nvsram Cell With A Charge-follower App 20140119119 - Lee; Peter Wung	2014-05-01
Nvsram Cells With Voltage Flash Charger App 20140119120 - Lee; Peter Wung	2014-05-01
8t Nvsram Cell And Cell Operations App 20140119118 - Lee; Peter Wung ; et al.	2014-05-01
10t Nvsram Cell And Cell Operations App 20140112072 - Tsao; Hsing-Ya ; et al.	2014-04-24
On-chip Hv And Lv Capacitors Acting As The Second Back-up Supplies For Nvsram Auto-store Operation App 20140104946 - Lee; Peter Wung ; et al.	2014-04-17
Method And Architecture For Improving Defect Detectability, Coupling Area, And Flexibility Of Nvsram Cells And Arrays App 20140085978 - Lee; Peter Wung	2014-03-27
Low-voltage Fast-write Pmos Nvsram Cell App 20140050025 - Tsao; Hsing-Ya ; et al.	2014-02-20
Universal timing waveforms sets to improve random access read and write speed of memories Grant 8,634,241 - Lee , et al. January 21, 2	2014-01-21
Single-polycrystalline silicon electrically erasable and programmable memory device of varied gate oxide thickness, using PIP or MIM coupling capacitor for cell size reduction and simultaneous VPP and VNN for write voltage reduction Grant 8,634,254 - Hsu , et al. January 21, 2	2014-01-21
Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory Grant 8,582,363 - Lee November 12, 2	2013-11-12
Low-voltage Fast-write Nvsram Cell App 20130294161 - Lee; Peter Wung ; et al.	2013-11-07
Novel Shielding 2-cycle Half-page Read And Program Schemes For Advanced Nand Flash Design App 20130279251 - Lee; Peter Wung	2013-10-24
Non-boosting Program Inhibit Scheme In Nand Design App 20130272067 - Lee; Peter Wung ; et al.	2013-10-17
DRAM-like NVM memory array and sense amplifier design for high temperature and high endurance operation Grant 8,559,232 - Lee , et al. October 15, 2	2013-10-15
Embedded NOR Flash Memory Process with NAND Cell and True Logic Compatible Low Voltage Device App 20130267067 - Lee; Peter Wung ; et al.	2013-10-10
NAND-based 2T2b NOR flash array with a diode connection to cell's source node for size reduction using the least number of metal layers Grant 8,531,885 - Hsu , et al. September 10, 2	2013-09-10
Three-Dimensional Flash-Based Combo Memory and Logic Design App 20130215683 - Lee; Peter Wung ; et al.	2013-08-22
NEW 1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN App 20130182509 - Lee; Peter Wung ; et al.	2013-07-18
Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device Grant 8,472,251 - Lee , et al. June 25, 2	2013-06-25
Cell array for highly-scalable, byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory Grant 8,462,553 - Lee , et al. June 11, 2	2013-06-11
Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device Grant 8,455,923 - Lee , et al. June 4, 2	2013-06-04
Low-Voltage Page Buffer to be Used in NVM Design App 20130128667 - Lee; Peter Wung ; et al.	2013-05-23
NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array Grant 8,345,481 - Lee , et al. January 1, 2	2013-01-01
Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array Grant 8,335,108 - Lee , et al. December 18, 2	2012-12-18
Integrated SRAM and FLOTOX EEPROM memory device Grant 8,331,150 - Hsu , et al. December 11, 2	2012-12-11
Novel High Speed High Density Nand-based 2t-nor Flash Memory Design App 20120268989 - Lee; Peter Wung ; et al.	2012-10-25
Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/- 10v BVDS Grant 8,295,087 - Lee , et al. October 23, 2	2012-10-23
Novel High Speed High Density NAND-Based 2T-NOR Flash Memory Design App 20120261741 - Lee; Peter Wung ; et al.	2012-10-18
Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array Grant 8,289,775 - Lee , et al. October 16, 2	2012-10-16
Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS Grant 8,274,829 - Lee , et al. September 25, 2	2012-09-25
Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory App 20120195123 - Lee; Peter Wung	2012-08-02
High speed high density NAND-based 2T-NOR flash memory design Grant 8,233,320 - Lee , et al. July 31, 2	2012-07-31
One-Die Flotox-Based Combo Non-Volatile Memory App 20120191902 - Lee; Peter Wung ; et al.	2012-07-26
Flexible 2T-Based Fuzzy and Certain Matching Arrays App 20120176841 - Lee; Peter Wung ; et al.	2012-07-12
Universal Timing Waveforms Sets to Improve Random Access Read and Write Speed of Memories App 20120155173 - LEE; Peter Wung ; et al.	2012-06-21
Write BIAS condition for 2T-string NOR flash cell App 20120087190 - Lee; Peter Wung ; et al.	2012-04-12
Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage Grant 8,149,622 - Lee , et al. April 3, 2	2012-04-03
Different types of memory integrated in one chip by using a novel protocol App 20120072647 - Lee; Peter Wung ; et al.	2012-03-22
EEPROM-based, data-oriented combo NVM design App 20120069651 - Lee; Peter Wung ; et al.	2012-03-22
Most compact flotox-based combo NVM design without sacrificing EEPROM endurance cycles for 1-die data and code storage App 20120063223 - Lee; Peter Wung ; et al.	2012-03-15
EEPROM-based, data-oriented combo NVM design App 20120063233 - Lee; Peter Wung ; et al.	2012-03-15
NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS flash memory array App 20120044770 - Lee; Peter Wung ; et al.	2012-02-23
NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same Grant 8,120,959 - Lee , et al. February 21, 2	2012-02-21
Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory Grant 8,120,966 - Lee February 21, 2	2012-02-21
Novel high-temperature non-volatile memory design App 20120020157 - Lee; Peter Wung ; et al.	2012-01-26
Novel embedded NOR flash memory process with NAND cell and true logic compatible low voltage device App 20120001233 - Lee; Peter Wung ; et al.	2012-01-05
NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array Grant 8,072,811 - Lee , et al. December 6, 2	2011-12-06
NAND-BASED 2T2b NOR FLASH ARRAY WITH A DIODE CONNECTION TO CELL'S SOURCE NODE FOR SIZE REDUCTION USING THE LEAST NUMBER OF METAL LAYERS App 20110292738 - Hsu; Fu-Chang ; et al.	2011-12-01
Dram-like Nvm Memory Array And Sense Amplifier Design For High Temperature And High Endurance Operation App 20110267883 - LEE; PETER WUNG ; et al.	2011-11-03
Single-Polycrystalline Silicon Electrically Erasable and Programmable Memory Device of Varied Gate Oxide Thickness, Using PIP or MIM Coupling Capacitor for Cell Size Reduction and Simultaneous VPP and VNN for Write Voltage Reduction App 20110235437 - Hsu; Fu-Chang ; et al.	2011-09-29
Flotox-based, Bit-alterable, Combo Flash And Eeprom Memory App 20110199830 - Lee; Peter Wung ; et al.	2011-08-18
Novel cell array for highly-scalable , byte-alterable, two-transistor FLOTOX EEPROM non-volatile memory App 20110157974 - Lee; Peter Wung ; et al.	2011-06-30
Novel High Speed High Density NAND-Based 2T-NOR Flash Memory Design App 20110157982 - Lee; Peter Wung ; et al.	2011-06-30
Novel punch-through free program scheme for nt-string flash design App 20110096609 - Lee; Peter Wung ; et al.	2011-04-28
Universal dual charge-retaining transistor flash NOR cell, a dual charge-retaining transistor flash NOR cell array, and method for operating same App 20110085382 - Lee; Peter Wung ; et al.	2011-04-14
Novel high speed two transistor/two bit NOR read only memory App 20110013443 - Lee; Peter Wung ; et al.	2011-01-20
Memory System Having Nand-based Nor And Nand Flashes And Sram Integrated In One Chip For Hybrid Data, Code And Cache Storage App 20100329011 - Lee; Peter Wung ; et al.	2010-12-30
Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array Grant 7,830,713 - Lee , et al. November 9, 2	2010-11-09
Method and apparatus for management of over-erasure in NAND-based NOR-type Flash Memory App 20100195404 - Lee; Peter Wung	2010-08-05
Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array App 20100124118 - Lee; Peter Wung ; et al.	2010-05-20
Bit line structure for a multilevel, dual-sided nonvolatile memory cell array Grant 7,688,612 - Lee , et al. March 30, 2	2010-03-30
Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array App 20090316487 - Lee; Peter Wung ; et al.	2009-12-24
NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same App 20090310414 - Lee; Peter Wung ; et al.	2009-12-17
Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/-10v BVDS App 20090310405 - Lee; Peter Wung ; et al.	2009-12-17
Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS App 20090310411 - Lee; Peter Wung ; et al.	2009-12-17
NAND based NMOS NOR flash memory cell, a NAND based NMOS nor flash memory array, and a method of forming a NAND based NMOS NOR flash memory array App 20090279360 - Lee; Peter Wung ; et al.	2009-11-12
Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device App 20090201742 - Lee; Peter Wung ; et al.	2009-08-13
Integrated SRAM and FLOTOX EEPROM memory device App 20090190402 - Hsu; Fu-Chang ; et al.	2009-07-30
Bit line structure for a multilevel, dual-sided nonvolatile memory cell array App 20080253186 - Lee; Peter Wung ; et al.	2008-10-16
Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array App 20080225594 - Lee; Peter Wung ; et al.	2008-09-18
NAND-type flash memory device with high voltage PMOS and embedded poly and methods of fabricating the same App 20070133289 - Ma; Han-Rei ; et al.	2007-06-14
Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation Grant 6,381,670 - Lee , et al. April 30, 2	2002-04-30
Charge pump circuits Grant 5,978,283 - Hsu , et al. November 2, 1	1999-11-02
Flash memory protection attribute status bits held in a flash memory array Grant 5,930,826 - Lee , et al. July 27, 1	1999-07-27
Flash memory array and decoding architecture Grant 5,777,924 - Lee , et al. July 7, 1	1998-07-07