| Patent | Date |
|---|
NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface
Grant 8,996,785 - Lee , et al. March 31, 2 | 2015-03-31 |
NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface
Grant 8,775,719 - Lee , et al. July 8, 2 | 2014-07-08 |
Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device
Grant 8,355,287 - Hsu , et al. January 15, 2 | 2013-01-15 |
Nonvolatile memory with a unified cell structure
Grant 8,237,212 - Lee , et al. August 7, 2 | 2012-08-07 |
Nonvolatile Memory With A Unified Cell Structure
App 20110170357 - Lee; Peter W. ; et al. | 2011-07-14 |
Nonvolatile memory with a unified cell structure
Grant 7,915,092 - Lee , et al. March 29, 2 | 2011-03-29 |
Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface
App 20110072200 - Lee; Peter W. ; et al. | 2011-03-24 |
Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface
App 20110072201 - Lee; Peter W. ; et al. | 2011-03-24 |
Novel NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with serial interface
App 20110051519 - Lee; Peter W. ; et al. | 2011-03-03 |
Method and apparatus for operation of a NAND-like dual charge retaining transistor NOR flash memory device
App 20110051524 - Hsu; Fu-Chang ; et al. | 2011-03-03 |
Nonvolatile memory with a unified cell structure
Grant 7,636,252 - Lee , et al. December 22, 2 | 2009-12-22 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
App 20080247230 - Lee; Peter W. ; et al. | 2008-10-09 |
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Grant 7,372,736 - Lee , et al. May 13, 2 | 2008-05-13 |
Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications
Grant 7,369,438 - Lee May 6, 2 | 2008-05-06 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
App 20080096327 - Lee; Peter W. ; et al. | 2008-04-24 |
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
Grant 7,349,257 - Lee , et al. March 25, 2 | 2008-03-25 |
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
Grant 7,339,824 - Lee , et al. March 4, 2 | 2008-03-04 |
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Grant 7,324,384 - Lee , et al. January 29, 2 | 2008-01-29 |
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Grant 7,289,366 - Lee , et al. October 30, 2 | 2007-10-30 |
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Grant 7,283,401 - Lee , et al. October 16, 2 | 2007-10-16 |
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
App 20070133341 - Lee; Peter W. ; et al. | 2007-06-14 |
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
App 20070076480 - Lee; Peter W. ; et al. | 2007-04-05 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
App 20070047302 - Lee; Peter W. ; et al. | 2007-03-01 |
Combination nonvolatile integrated memory system using a universal technology most suitable for high-density, high-flexibility and high-security sim-card, smart-card and e-passport applications
Grant 7,177,190 - Lee February 13, 2 | 2007-02-13 |
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
Grant 7,154,783 - Lee , et al. December 26, 2 | 2006-12-26 |
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
Grant 7,149,120 - Lee , et al. December 12, 2 | 2006-12-12 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
App 20060234394 - Lee; Peter W. ; et al. | 2006-10-19 |
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Grant 7,120,064 - Lee , et al. October 10, 2 | 2006-10-10 |
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Grant 7,110,302 - Lee , et al. September 19, 2 | 2006-09-19 |
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Grant 7,102,929 - Lee , et al. September 5, 2 | 2006-09-05 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
App 20060176738 - Lee; Peter W. ; et al. | 2006-08-10 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
App 20060176739 - Lee; Peter W. ; et al. | 2006-08-10 |
Unified non-volatile memory device and method for integrating NOR and NAND-type flash memory and EEPROM device on a single substrate
Grant 7,087,953 - Lee August 8, 2 | 2006-08-08 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
App 20060171203 - Lee; Peter W. ; et al. | 2006-08-03 |
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Grant 7,075,826 - Lee , et al. July 11, 2 | 2006-07-11 |
Novel combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications
App 20060138245 - Lee; Peter W. | 2006-06-29 |
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Grant 7,064,978 - Lee , et al. June 20, 2 | 2006-06-20 |
Unified Non-volatile Memory Device And Method For Integrating Nor And Nand-type Flash Memory And Eeprom Device On A Single Substrate
App 20060118854 - Lee; Peter W. | 2006-06-08 |
Novel combination nonvolatile integrated memory system using a universal technology most suitable for high-density, high-flexibility and high-security sim-card, smart-card and e-passport applications
App 20060114719 - Lee; Peter W. | 2006-06-01 |
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
App 20050185501 - Lee, Peter W. ; et al. | 2005-08-25 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
App 20050162910 - Lee, Peter W. ; et al. | 2005-07-28 |
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
App 20050141298 - Lee, Peter W. ; et al. | 2005-06-30 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
App 20050135152 - Lee, Peter W. ; et al. | 2005-06-23 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
App 20050122776 - Lee, Peter W. ; et al. | 2005-06-09 |
Array architecture and process flow of nonvolatile memory devices for mass storage applications
Grant 6,891,221 - Lee , et al. May 10, 2 | 2005-05-10 |
Monolithic, Combo Nonvolatile Memory Allowing Byte, Page And Block Write With No Disturb And Divided-well In The Cell Array Using A Unified Cell Structure And Technology With A New Scheme Of Decoder And Layout
Grant 6,862,223 - Lee , et al. March 1, 2 | 2005-03-01 |
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
Grant 6,850,438 - Lee , et al. February 1, 2 | 2005-02-01 |
Set of three level concurrent word line bias conditions for a NOR type flash memory array
Grant 6,818,491 - Lee , et al. November 16, 2 | 2004-11-16 |
Flash memory array structure suitable for multiple simultaneous operations
Grant 6,788,612 - Hsu , et al. September 7, 2 | 2004-09-07 |
Flash memory array structure suitable for multiple simultaneous operations
Grant 6,788,611 - Hsu , et al. September 7, 2 | 2004-09-07 |
Array architecture and process flow of nonvolatile memory devices for mass storage applications
App 20040166634 - Lee, Peter W. ; et al. | 2004-08-26 |
Array architecture and process flow of nonvolatile memory devices for mass storage applications
App 20040165459 - Lee, Peter W. ; et al. | 2004-08-26 |
Set of three level concurrent word line bias conditions for a NOR type flash memory array
Grant 6,777,292 - Lee , et al. August 17, 2 | 2004-08-17 |
Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device
Grant 6,757,196 - Tsao , et al. June 29, 2 | 2004-06-29 |
Non-volatile semiconductor memory having split-gate memory cells mirrored in a virtual ground configuration
Grant 6,717,846 - Lee , et al. April 6, 2 | 2004-04-06 |
Parallel channel programming scheme for MLC flash memory
Grant 6,714,457 - Hsu , et al. March 30, 2 | 2004-03-30 |
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
App 20040047203 - Lee, Peter W. ; et al. | 2004-03-11 |
Novel set of three level concurrent word line bias conditions for a NOR type flash memory array
App 20040027894 - Lee, Peter W. ; et al. | 2004-02-12 |
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations
App 20040027856 - Lee, Peter W. ; et al. | 2004-02-12 |
Novel set of three level concurrent word line bias conditions for a NOR type flash memory array
App 20040029335 - Lee, Peter W. ; et al. | 2004-02-12 |
Highly-integrated flash memory and mask ROM array architecture
Grant 6,687,154 - Lee , et al. February 3, 2 | 2004-02-03 |
Stacked gate flash memory cell with reduced distrub conditions
App 20040008561 - Lee, Peter W. ; et al. | 2004-01-15 |
Stacked gate flash memory cell with reduced disturb conditions
Grant 6,660,585 - Lee , et al. December 9, 2 | 2003-12-09 |
Novel flash memory array structure suitable for multiple simultaneous operations
App 20030206456 - Hsu, Fu-Chang ; et al. | 2003-11-06 |
Novel flash memory array structure suitable for multiple simultaneous operations
App 20030206455 - Hsu, Fu-Chang ; et al. | 2003-11-06 |
Flash memory array for multiple simultaneous operations
Grant 6,628,563 - Hsu , et al. September 30, 2 | 2003-09-30 |
Set of three level concurrent word line bias conditions for a nor type flash memory array
Grant 6,620,682 - Lee , et al. September 16, 2 | 2003-09-16 |
Novel highly-integrated flash memory and mask ROM array architecture
App 20030161184 - Lee, Peter W. ; et al. | 2003-08-28 |
3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell
Grant 6,556,481 - Hsu , et al. April 29, 2 | 2003-04-29 |
Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM
Grant 6,515,910 - Lee , et al. February 4, 2 | 2003-02-04 |
Three step write process used for a nonvolatile NOR type EEPROM memory
Grant 6,498,752 - Hsu , et al. December 24, 2 | 2002-12-24 |
Apparatus for improving film stability of halogen-doped silicon oxide films
Grant 6,374,770 - Lee , et al. April 23, 2 | 2002-04-23 |
Method and apparatus for elimination of TEOS/ozone silicon oxide surface sensitivity
Grant 6,319,324 - Nguyen , et al. November 20, 2 | 2001-11-20 |
Array architecture and process flow of nonvolatile memory devices for mass storage applications
Grant 6,258,668 - Lee , et al. July 10, 2 | 2001-07-10 |
Method for elimination of TEOS/ozone silicon oxide surface sensitivity
Grant 6,149,974 - Nguyen , et al. November 21, 2 | 2000-11-21 |
Erase condition for flash memory
Grant 6,134,150 - Hsu , et al. October 17, 2 | 2000-10-17 |
Method and apparatus for improving film stability of halogen-doped silicon oxide films
Grant 6,103,601 - Lee , et al. August 15, 2 | 2000-08-15 |
Positive/negative high voltage charge pump system
Grant 6,023,188 - Lee , et al. February 8, 2 | 2000-02-08 |
Node-precise voltage regulation for a MOS memory system
Grant 6,009,022 - Lee , et al. December 28, 1 | 1999-12-28 |
Method and apparatus for forming a thin polymer layer on an integrated circuit structure
Grant 5,958,510 - Sivaramakrishnam , et al. September 28, 1 | 1999-09-28 |
Flash memory with novel bitline decoder and sourceline latch
Grant 5,920,503 - Lee , et al. July 6, 1 | 1999-07-06 |
Flash memory with high speed erasing structure using thin oxide semiconductor devices
Grant 5,917,757 - Lee , et al. June 29, 1 | 1999-06-29 |
Flash memory with high speed erasing structure using thin oxide and thick oxide semiconductor devices
Grant 5,914,896 - Lee , et al. June 22, 1 | 1999-06-22 |
Flash memory address decoder with novel latch structure
Grant 5,848,000 - Lee , et al. December 8, 1 | 1998-12-08 |
Flash memory wordline decoder with overerase repair
Grant 5,822,252 - Lee , et al. October 13, 1 | 1998-10-13 |
Flash memory with flexible erasing size from multi-byte to multi-block
Grant 5,796,657 - Lee , et al. August 18, 1 | 1998-08-18 |
Flash memory read/write controller
Grant 5,777,923 - Lee , et al. July 7, 1 | 1998-07-07 |
Bit-refreshable method and circuit for refreshing a nonvolatile flash memory
Grant 5,768,193 - Lee , et al. June 16, 1 | 1998-06-16 |
OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array
Grant 5,748,538 - Lee , et al. May 5, 1 | 1998-05-05 |
Memory device with on-chip manufacturing and memory cell defect detection capability
Grant 5,748,545 - Lee , et al. May 5, 1 | 1998-05-05 |
Flash EEPROM worldline decoder
Grant 5,687,121 - Lee , et al. November 11, 1 | 1997-11-11 |
Flash memory with divided bitline
Grant 5,682,350 - Lee , et al. October 28, 1 | 1997-10-28 |
Flexible byte-erase flash memory and decoder
Grant 5,646,890 - Lee , et al. July 8, 1 | 1997-07-08 |
Flat-cell ROM and decoder
Grant 5,600,586 - Lee February 4, 1 | 1997-02-04 |
Two step process for forming void-free oxide layer over stepped surface of semiconductor wafer
Grant 5,314,845 - Lee , et al. May 24, 1 | 1994-05-24 |
Method of making a machine component with lubricated wear surface
Grant 5,309,639 - Lee May 10, 1 | 1994-05-10 |
Method for forming a boron phosphorus silicate glass composite layer on a semiconductor wafer
Grant 5,166,101 - Lee , et al. November 24, 1 | 1992-11-24 |
Electrical drive circuit for a variable-speed switched reluctance motor
Grant 4,731,570 - Lee March 15, 1 | 1988-03-15 |
Powder metal composite and method of its manufacture
Grant 4,721,598 - Lee January 26, 1 | 1988-01-26 |
Tapered roller bearing capable of sustained operation without lubricant replenishment
Grant 4,601,592 - Jatczak , et al. July 22, 1 | 1986-07-22 |
Tapered roller bearing with pressurized rib ring
Grant 4,571,097 - Lee , et al. February 18, 1 | 1986-02-18 |
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