loadpatents
name:-0.003187894821167
name:-0.010092973709106
name:-0.00046801567077637
Lee; Kong Hean Patent Filings

Lee; Kong Hean

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lee; Kong Hean.The latest application filed is for "silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts".

Company Profile
0.10.1
  • Lee; Kong Hean - Singapore SG
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method to form shallow trench isolations
Grant 6,649,486 - Balakumar , et al. November 18, 2
2003-11-18
Shallow trench isolation using TEOS cap and polysilicon pullback
Grant 6,613,648 - Lim , et al. September 2, 2
2003-09-02
Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions
Grant 6,410,429 - Ho , et al. June 25, 2
2002-06-25
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts
Grant 6,350,661 - Lim , et al. February 26, 2
2002-02-26
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts
App 20010031540 - Lim, Chong Wee ;   et al.
2001-10-18
Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts
Grant 6,297,126 - Lim , et al. October 2, 2
2001-10-02
Partially recessed shallow trench isolation method for fabricating borderless contacts
Grant 6,265,302 - Lim , et al. July 24, 2
2001-07-24
Method for forming a shallow trench isolation using HDP silicon oxynitride
Grant 6,258,676 - Lee , et al. July 10, 2
2001-07-10
Method to form shallow trench isolations with rounded corners and reduced trench oxide recess
Grant 6,228,727 - Lim , et al. May 8, 2
2001-05-08
Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device
Grant 6,165,871 - Lim , et al. December 26, 2
2000-12-26
Cmos gate architecture for integration of salicide process in sub 0.1 . .muM devices
Grant 6,010,954 - Ho , et al. January 4, 2
2000-01-04

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