Patent | Date |
---|
Physical design system and method Grant 8,473,885 - Cohn , et al. June 25, 2 | 2013-06-25 |
Physical design system and method Grant 8,219,943 - Cohn , et al. July 10, 2 | 2012-07-10 |
Physical Design System And Method App 20120167029 - Cohn; John M. ;   et al. | 2012-06-28 |
Optimizing integrated circuit chip designs for optical proximity correction Grant 8,122,387 - Han , et al. February 21, 2 | 2012-02-21 |
Layout quality gauge for integrated circuit design Grant 8,020,120 - Heng , et al. September 13, 2 | 2011-09-13 |
Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields App 20110173577 - Chuang; Ching-Te K. ;   et al. | 2011-07-14 |
System and method for employing patterning process statistics for ground rules waivers and optimization Grant 7,962,865 - Heng , et al. June 14, 2 | 2011-06-14 |
Method Of Integrated Circuit Chip Fabrication And Program Product Therefor App 20100318956 - Han; Geng ;   et al. | 2010-12-16 |
CA resistance variability prediction methodology Grant 7,831,941 - Chidambarrao , et al. November 9, 2 | 2010-11-09 |
Iphysical Design System And Method App 20090204930 - Cohn; John M. ;   et al. | 2009-08-13 |
Ca Resistance Variability Prediction Methodology App 20090171644 - Chidambarrao; Dureseti ;   et al. | 2009-07-02 |
Physical design system and method Grant 7,536,664 - Cohn , et al. May 19, 2 | 2009-05-19 |
Layout Quality Gauge for Integrated Circuit Design App 20090089726 - Heng; Fook-Luen ;   et al. | 2009-04-02 |
System And Method For Employing Patterning Process Statistics For Ground Rules Waivers And Optimization App 20080301624 - Heng; Fook-Luen ;   et al. | 2008-12-04 |
System and method for employing patterning process statistics for ground rules waivers and optimization Grant 7,448,018 - Heng , et al. November 4, 2 | 2008-11-04 |
System and method for employing patterning process statistics for ground rules waivers and optimization App 20080066047 - Heng; Fook-Luen ;   et al. | 2008-03-13 |
Integrated circuit logic with self compensating shapes Grant 7,302,671 - Heng , et al. November 27, 2 | 2007-11-27 |
Lithographic process window optimization under complex constraints on edge placement Grant 7,269,817 - Heng , et al. September 11, 2 | 2007-09-11 |
Physical design system and method App 20060036977 - Cohn; John M. ;   et al. | 2006-02-16 |
Integrated circuit logic with self compensating shapes App 20050189605 - Heng, Fook-Luen ;   et al. | 2005-09-01 |
Lithographic process window optimization under complex constraints on edge placement App 20050177810 - Heng, Fook-Luen ;   et al. | 2005-08-11 |
Methods and apparatus for performing slew dependent signal bounding for signal timing analysis Grant 6,430,731 - Lee , et al. August 6, 2 | 2002-08-06 |
Clock distribution network with dual wire routing Grant 6,144,224 - Lee , et al. November 7, 2 | 2000-11-07 |