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Computer memory module processing device with cache storage
Grant 11,442,866 - Ke , et al. September 13, 2 | 2022-09-13 |
Memory Circuit and Cache Circuit Configuration
App 20220129382 - Lee; Hsien-Hsin Sean ; et al. | 2022-04-28 |
Integrated Circuit And Method Of Manufacturing The Same
App 20220027545 - CHANG; Yu-Jung ; et al. | 2022-01-27 |
Memory circuit and cache circuit configuration
Grant 11,216,376 - Lee , et al. January 4, 2 | 2022-01-04 |
Standard Cell And Semiconductor Device Including Anchor Nodes And Method Of Making
App 20210365623 - TSAI; Nien-Yu ; et al. | 2021-11-25 |
Integrated circuit and system of manufacturing the same
Grant 11,138,361 - Chang , et al. October 5, 2 | 2021-10-05 |
Multi-patterning Graph Reduction And Checking Flow Method
App 20210279398 - TSAI; Nien-Yu ; et al. | 2021-09-09 |
Standard cell and semiconductor device including anchor nodes and method of making
Grant 11,106,852 - Tsai , et al. August 31, 2 | 2021-08-31 |
Integrated circuit and method for manufacturing same
Grant 11,062,075 - Chang , et al. July 13, 2 | 2021-07-13 |
Computer Memory Module Processing Device With Cache Storage
App 20210191871 - Ke; Liu ; et al. | 2021-06-24 |
Multi-patterning graph reduction and checking flow method
Grant 11,017,148 - Tsai , et al. May 25, 2 | 2021-05-25 |
Method of determining colorability of a semiconductor device and system for implementing the same
Grant 10,878,167 - Cheng , et al. December 29, 2 | 2020-12-29 |
Standard Cell And Semiconductor Device Including Anchor Nodes And Method Of Making
App 20200311333 - TSAI; Nien-Yu ; et al. | 2020-10-01 |
Standard cell and semiconductor device including anchor nodes
Grant 10,713,407 - Tsai , et al. | 2020-07-14 |
Multi-patterning Graph Reduction And Checking Flow Method
App 20200167519 - TSAI; Nien-Yu ; et al. | 2020-05-28 |
Method Of Determining Colorability Of A Semiconductor Device And System For Implementing The Same
App 20200117848 - CHENG; Chung-Yun ; et al. | 2020-04-16 |
Integrated Circuit And System Of Manufacturing The Same
App 20200097630 - CHANG; Yu-Jung ; et al. | 2020-03-26 |
Integrated Circuit And Method For Manufacturing Same
App 20200097629 - CHANG; Yu-Jung ; et al. | 2020-03-26 |
Memory Circuit and Cache Circuit Configuration
App 20200026648 - Lee; Hsien-Hsin Sean ; et al. | 2020-01-23 |
Method of determining colorability of a semiconductor device and system for implementing the same
Grant 10,515,185 - Cheng , et al. Dec | 2019-12-24 |
Method for layout generation with constrained hypergraph partitioning
Grant 10,509,883 - Yang , et al. Dec | 2019-12-17 |
Integrated circuit and method for manufacturing the same
Grant 10,489,548 - Chang , et al. Nov | 2019-11-26 |
Multi-patterning graph reduction and checking flow method
Grant 10,430,544 - Tsai , et al. O | 2019-10-01 |
Memory circuit and cache circuit configuration
Grant 10,430,334 - Lee , et al. O | 2019-10-01 |
Method Of Determining Colorability Of A Semiconductor Device And System For Implementing The Same
App 20190171789 - CHENG; Chung-Yun ; et al. | 2019-06-06 |
Standard Cell And Semiconductor Device Including Anchor Nodes
App 20190130061 - TSAI; Nien-Yu ; et al. | 2019-05-02 |
Method of determining colorability of a semiconductor device and system for implementing the same
Grant 10,204,205 - Cheng , et al. Feb | 2019-02-12 |
Method of designing a semiconductor device, system for implementing the method and standard cell
Grant 10,162,928 - Tsai , et al. Dec | 2018-12-25 |
Integrated Circuit And Method For Manufacturing The Same
App 20180341735 - CHANG; Yu-Jung ; et al. | 2018-11-29 |
Method, device and computer program product for integrated circuit layout generation
Grant 10,140,407 - Ho , et al. Nov | 2018-11-27 |
Method of generating modified layout and system therefor
Grant 10,019,548 - Ho , et al. July 10, 2 | 2018-07-10 |
Method For Layout Generation With Constrained Hypergraph Partitioning
App 20180150585 - YANG; Tsun-Yu ; et al. | 2018-05-31 |
Multi-patterning Graph Reduction And Checking Flow Method
App 20180068049 - TSAI; Nien-Yu ; et al. | 2018-03-08 |
Mask design based on sensitivities to changes in pattern spacing
Grant 9,846,761 - Chou , et al. December 19, 2 | 2017-12-19 |
Method Of Generating Modified Layout And System Therefor
App 20170316142 - HO; Chia-Ming ; et al. | 2017-11-02 |
Method of generating modified layout for RC extraction
Grant 9,710,588 - Ho , et al. July 18, 2 | 2017-07-18 |
Method Of Determining Colorability Of A Semiconductor Device And System For Implementing The Same
App 20170199957 - CHENG; Chung-Yun ; et al. | 2017-07-13 |
Method Of Designing A Semiconductor Device, System For Implementing The Method And Standard Cell
App 20170161424 - TSAI; Nien-Yu ; et al. | 2017-06-08 |
Multi-layer semiconductor structures for fabricating inverter chains
Grant 9,666,490 - Lin , et al. May 30, 2 | 2017-05-30 |
System and method for creating hybrid resistance and capacitance (RC) netlist using three-dimensional RC extraction and 2.5 dimensional RC extraction
Grant 9,582,630 - Wu , et al. February 28, 2 | 2017-02-28 |
Mask Design Based On Sensitivities To Changes In Pattern Spacing
App 20170004252 - CHOU; Chih-Cheng ; et al. | 2017-01-05 |
Memory Circuit and Cache Circuit Configuration
App 20160364331 - Lee; Hsien-Hsin Sean ; et al. | 2016-12-15 |
Method and apparatus for capacitance extraction
Grant 9,471,738 - Chou , et al. October 18, 2 | 2016-10-18 |
Multi-layer Semiconductor Structures For Fabricating Inverter Chains
App 20160284603 - Lin; I-Fan ; et al. | 2016-09-29 |
Mask shift resistance-inductance method for multiple patterning mask design and a method for performing the same
Grant 9,448,467 - Chou , et al. September 20, 2 | 2016-09-20 |
Memory circuit and cache circuit configuration
Grant 9,431,064 - Lee , et al. August 30, 2 | 2016-08-30 |
Method And Apparatus For Capacitance Extraction
App 20160232270 - CHOU; Chih-Cheng ; et al. | 2016-08-11 |
Multi-layer semiconductor structures for fabricating inverter chains
Grant 9,373,623 - Lin , et al. June 21, 2 | 2016-06-21 |
Method, Device And Computer Program Product For Integrated Circuit Layout Generation
App 20160147928 - HO; Chia-Ming ; et al. | 2016-05-26 |
Method and system for verifying the design of an integrated circuit having multiple tiers
Grant 9,330,215 - Tsai , et al. May 3, 2 | 2016-05-03 |
Cell Based Hybrid Rc Extraction
App 20160063165 - Wu; Ze-Ming ; et al. | 2016-03-03 |
Method Of Generating Modified Layout For Rc Extraction
App 20160042108 - HO; Chia-Ming ; et al. | 2016-02-11 |
Method And System For Verifying The Design Of An Integrated Circuit Having Multiple Tiers
App 20150269303 - TSAI; Yao-Hsien ; et al. | 2015-09-24 |
Mask Shift Resistance-inductance Method For Multiple Patterning Mask Design And A Method For Performing The Same
App 20150234975 - CHOU; Chih-Cheng ; et al. | 2015-08-20 |
Multi-layer Semiconductor Structures For Fabricating Inverter Chains
App 20150179648 - LIN; I-FAN ; et al. | 2015-06-25 |
Systems and methods for tuning technology files
Grant 9,003,345 - Wu , et al. April 7, 2 | 2015-04-07 |
Multi-patterning mask decomposition method and system
Grant 8,954,900 - Ho , et al. February 10, 2 | 2015-02-10 |
Multi-patterning Mask Decomposition Method And System
App 20150040077 - HO; Chia-Ming ; et al. | 2015-02-05 |
Systems And Methods For Tuning Technology Files
App 20140282342 - WU; Meng-Fan ; et al. | 2014-09-18 |
Parasitic Capacitance Extraction for FinFETs
App 20140258962 - Ho; Chia-Ming ; et al. | 2014-09-11 |
Parasitic capacitance extraction for FinFETs
Grant 8,826,213 - Ho , et al. September 2, 2 | 2014-09-02 |
Memory Circuit And Method Of Operating The Memory Circui
App 20140126274 - LEE; Hsien-Hsin Sean ; et al. | 2014-05-08 |
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