loadpatents
name:-0.0086231231689453
name:-0.0065040588378906
name:-0.0021889209747314
Lee; Hsiao-Chun Patent Filings

Lee; Hsiao-Chun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lee; Hsiao-Chun.The latest application filed is for "semiconductor device and method fabricating the same".

Company Profile
1.9.9
  • Lee; Hsiao-Chun - Chiayi TW
  • LEE; Hsiao-Chun - Chiayi City TW
  • Lee; Hsiao-Chun - Hsinchu TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor device and method fabricating the same
Grant 10,020,251 - Lee , et al. July 10, 2
2018-07-10
Semiconductor Device and Method Fabricating the Same
App 20170373002 - Lee; Hsiao-Chun ;   et al.
2017-12-28
Through Substrate Via Structure For Noise Reduction
App 20170358493 - FANG; Chun-Lin ;   et al.
2017-12-14
Through substrate via structure for noise reduction
Grant 9,842,774 - Fang , et al. December 12, 2
2017-12-12
Bipolar junction transistor layout
Grant 9,780,089 - Tsai , et al. October 3, 2
2017-10-03
Semiconductor device and method fabricating the same
Grant 9,768,112 - Lee , et al. September 19, 2
2017-09-19
Semiconductor device with guard ring coupled resonant circuit
Grant 9,705,466 - Chen , et al. July 11, 2
2017-07-11
Bipolar Junction Transistor Layout
App 20170047323 - TSAI; Han-Min ;   et al.
2017-02-16
Bipolar junction transistor layout
Grant 9,484,408 - Tsai , et al. November 1, 2
2016-11-01
Semiconductor Device and Method Fabricating the Same
App 20160307841 - LEE; HSIAO-CHUN ;   et al.
2016-10-20
Semiconductor Device With Guard Ring Coupled Resonant Circuit
App 20160248394 - CHEN; Yen-Jen ;   et al.
2016-08-25
Semiconductor device and method fabricating the same
Grant 9,406,626 - Lee , et al. August 2, 2
2016-08-02
Semiconductor Device And Method Fabricating The Same
App 20150333019 - LEE; HSIAO-CHUN ;   et al.
2015-11-19
Dual DNW isolation structure for reducing RF noise on high voltage semiconductor devices
Grant 8,921,978 - Huang , et al. December 30, 2
2014-12-30
Structure and Method for an Inductor With Metal Dummy Features
App 20140252542 - Lee; Hsiao-Chun ;   et al.
2014-09-11
Dual Dnw Isolation Structure For Reducing Rf Noise On High Voltage Semiconductor Devices
App 20130175655 - HUANG; Chi-Feng ;   et al.
2013-07-11

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed