Lee; Herng-Jer

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lee; Herng-Jer.The latest application filed is for "interconnect model-order reduction method".

Company Profile

0.10.11

Lee; Herng-Jer - Tao-Yuan TW
Lee; Herng-Jer - Kwei-Shan TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Generalizations of adjoint networks techniques for RLC interconnects model-order reductions Grant 7,797,140 - Lee , et al. September 14, 2	2010-09-14
Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders Grant 7,512,525 - Lee , et al. March 31, 2	2009-03-31
Interconnect model-order reduction method Grant 7,437,689 - Chu , et al. October 14, 2	2008-10-14
Efficient digital filter design tool for approximating an FIR filter with a low-order linear-phase IIR filter Grant 7,373,367 - Lee , et al. May 13, 2	2008-05-13
Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops Grant 7,254,790 - Lee , et al. August 7, 2	2007-08-07
Method and apparatus for model-order reduction and sensitivity analysis Grant 7,216,309 - Lee , et al. May 8, 2	2007-05-08
Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration Grant 7,191,418 - Lee , et al. March 13, 2	2007-03-13
Method on scan chain reordering for lowering VLSI power consumption Grant 7,181,664 - Lee , et al. February 20, 2	2007-02-20
Interconnect model-order reduction method App 20070033549 - Chu; Chia-Chi ; et al.	2007-02-08
Method of estimating crosstalk noise in lumped RLC coupled interconnects Grant 7,124,381 - Lee , et al. October 17, 2	2006-10-17
Multi-point model reductions of VLSI interconnects using the rational arnoldi method with adaptive orders App 20060149525 - Lee; Herng-Jer ; et al.	2006-07-06
Generalizations of adjoint networks techniques for RLC interconnects model-order reductions App 20060100831 - Lee; Herng-Jer ; et al.	2006-05-11
Moment computations of nonuniform distributed coupled RLC trees with applications to estimating crosstalk noise App 20060100830 - Lee; Herng-Jer ; et al.	2006-05-11
Method of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits Grant 7,017,130 - Lee , et al. March 21, 2	2006-03-21
Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops App 20060015832 - Lee; Herng-Jer ; et al.	2006-01-19
Method Of Verification Of Estimating Crosstalk Noise In Coupled Rlc Interconnects With Distributed Line In Nanometer Integrated Circuits App 20060010406 - Lee; Herng-Jer ; et al.	2006-01-12
Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration App 20060010414 - Lee; Herng-Jer ; et al.	2006-01-12
Method of estimating crosstalk noise in lumped RLC coupled interconnects App 20050278668 - Lee, Herng-Jer ; et al.	2005-12-15
Method on scan chain reordering for lowering VLSI power consumption App 20050235182 - Lee, Herng-Jer ; et al.	2005-10-20
Efficient digital filter design tool for approximating an FIR filter with a low-order linear-phase IIR filter App 20050235023 - Lee, Herng-Jer ; et al.	2005-10-20
Method and apparatus for model-order reduction and sensitivity analysis App 20040261042 - Lee, Herng-Jer ; et al.	2004-12-23

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