Lee; Guanru

Patent Applications and Registrations

Patent applications and USPTO patent grants for Lee; Guanru.The latest application filed is for "memory architecture of array with single gate memory devices".

Company Profile

0.9.9

Lee; Guanru - Hsinchu TW
Lee; Guanru - Kaohsiung TW
Lee; GuanRu - Kaohsiung City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory architecture of array with single gate memory devices Grant 9,397,113 - Lee July 19, 2	2016-07-19
Damascene conductor for a 3D device Grant 9,379,126 - Chiu , et al. June 28, 2	2016-06-28
Memory Architecture Of Array With Single Gate Memory Devices App 20160181270 - LEE; Guanru	2016-06-23
Memory architecture of 3D array with interleaved control structures Grant 9,356,037 - Lee May 31, 2	2016-05-31
Memory Architecture Of 3d Array With Interleaved Control Structures App 20160005746 - Lee; GuanRu	2016-01-07
Damascene conductor for 3D array Grant 9,123,778 - Lai , et al. September 1, 2	2015-09-01
Semiconductor device having polysilicon mask layer Grant 9,105,667 - Lee August 11, 2	2015-08-11
Damascene Conductor For 3d Array App 20140264546 - LAI; ERH-KUN ; et al.	2014-09-18
Mask Layer And Method Of Formation App 20140264352 - LEE; Guanru	2014-09-18
Damascene Conductor For A 3d Device App 20140264897 - CHIU; CHIAJUNG ; et al.	2014-09-18
Multi-level vertical plug formation with stop layers of increasing thicknesses Grant 8,736,069 - Chiu , et al. May 27, 2	2014-05-27
Multi-Level Vertical Plug Formation With Stop Layers of Increasing Thicknesses App 20140054789 - Chiu; Chiajung ; et al.	2014-02-27
Z-direction decoding for three dimensional memory array Grant 8,570,806 - Lee October 29, 2	2013-10-29
Z-Direction Decoding for Three Dimensional Memory Array App 20130148427 - Lee; Guanru	2013-06-13

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