Leas; James M.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Leas; James M..The latest application filed is for "carrier for test, burn-in, and first level packaging".
- Leas; James M. - South Burlington VT
- Leas; James M. - S. Burlington VT
- Leas, James M. - Burlington VT
- Leas; James M. - Chittenden County VT
- Leas; James M. - So. Burlington VT
- Leas; James M. - Bethesda MD
- Leas; James M. - Washington DC
| Patent | Date |
|---|---|
| Carrier for test, burn-in, and first level packaging Grant 7,394,268 - Bertin , et al. July 1, 2 | 2008-07-01 |
| Vertical dual gate field effect transistor Grant 7,176,089 - Furukawa , et al. February 13, 2 | 2007-02-13 |
| Carrier For Test, Burn-in, And First Level Packaging App 20070001708 - Bertin; Claude L. ; et al. | 2007-01-04 |
| Carrier for test, burn-in, and first level packaging Grant 7,132,841 - Bertin , et al. November 7, 2 | 2006-11-07 |
| SiGe or germanium flip chip optical receiver Grant 6,980,748 - Leas December 27, 2 | 2005-12-27 |
| Vertical dual gate field effect transistor App 20040219725 - Furukawa, Toshiharu ; et al. | 2004-11-04 |
| Vertical dual gate field effect transistor Grant 6,798,017 - Furukawa , et al. September 28, 2 | 2004-09-28 |
| SiGe or germanium flip chip optical receiver App 20030094699 - Leas, James M. | 2003-05-22 |
| Vertical dual gate field effect transistor App 20030052364 - Furukawa, Toshiharu ; et al. | 2003-03-20 |
| Structure for making sub-lithographic images by the intersection of two spacers Grant 5,920,101 - Beilstein, Jr. , et al. July 6, 1 | 1999-07-06 |
| Structure for making sub-lithographic images by the intersection of two spacers Grant 5,834,818 - Beilstein, Jr. , et al. November 10, 1 | 1998-11-10 |
| Method for making sub-lithographic images by etching the intersection of two spacers Grant 5,714,039 - Beilstein, Jr. , et al. February 3, 1 | 1998-02-03 |
| Optical FET with diode adjacent gate Grant 5,610,409 - Leas , et al. March 11, 1 | 1997-03-11 |
| Semiconductor wafer test and burn-in Grant 5,600,257 - Leas , et al. February 4, 1 | 1997-02-04 |
| Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging Grant 5,567,654 - Beilstein, Jr. , et al. October 22, 1 | 1996-10-22 |
| Optical fet Grant 5,557,114 - Leas , et al. September 17, 1 | 1996-09-17 |
| Electronic modules with interconnected surface metallization layers Grant 5,517,057 - Beilstein, Jr. , et al. May 14, 1 | 1996-05-14 |
| Electronic modules with interconnected surface metallization layers and fabrication methods therefore Grant 5,466,634 - Beilstein, Jr. , et al. November 14, 1 | 1995-11-14 |
| Method of making embedded integrated laser arrays and support circuits Grant 4,971,927 - Leas November 20, 1 | 1990-11-20 |
| Method and apparatus for causing an open circuit in a conductive line Grant 4,962,294 - Beckham , et al. October 9, 1 | 1990-10-09 |
| Solar cell metal spray process Grant 4,511,600 - Leas April 16, 1 | 1985-04-16 |
| Thin film semiconductor device and method for manufacture Grant 4,400,715 - Barbee , et al. August 23, 1 | 1983-08-23 |
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