| Patent | Date |
|---|
Method for manufacturing a fin MOS transistor
Grant 9,673,329 - Morand , et al. June 6, 2 | 2017-06-06 |
Low leakage dual STI integrated circuit including FDSOI transistors
Grant 9,601,511 - Vinet , et al. March 21, 2 | 2017-03-21 |
Dual STI integrated circuit including FDSOI transistors and method for manufacturing the same
Grant 9,570,465 - Vinet , et al. February 14, 2 | 2017-02-14 |
Method for fabricating microelectronic devices with isolation trenches partially formed under active regions
Grant 9,437,474 - Grenouillet , et al. September 6, 2 | 2016-09-06 |
Defective P-N junction for backgated fully depleted silicon on insulator mosfet
Grant 9,373,507 - Cheng , et al. June 21, 2 | 2016-06-21 |
Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same
Grant 9,337,350 - Posseme , et al. May 10, 2 | 2016-05-10 |
Method For Manufacturing A Fin Mos Transistor
App 20160087092 - Morand; Yves ; et al. | 2016-03-24 |
Dual channel hybrid semiconductor-on-insulator semiconductor devices
Grant 9,293,474 - Cheng , et al. March 22, 2 | 2016-03-22 |
Dual Sti Integrated Circuit Including Fdsoi Transistors And Method For Manufacturing The Same
App 20160013205 - VINET; Maud ; et al. | 2016-01-14 |
Low Leakage Dual Sti Integrated Circuit Including Fdsoi Transistors
App 20160013206 - VINET; Maud ; et al. | 2016-01-14 |
Method for manufacturing a fin MOS transistor
Grant 9,236,478 - Morand , et al. January 12, 2 | 2016-01-12 |
Method for treating the surface of a silicon substrate
Grant 9,231,062 - Le Tiec , et al. January 5, 2 | 2016-01-05 |
Method for making a semiconductor structure with a buried ground plane
Grant 9,214,515 - Le Tiec , et al. December 15, 2 | 2015-12-15 |
Method For Fabricating Microelectronic Devices With Isolation Trenches Partially Formed Under Active Regions
App 20150294903 - Grenouillet; Laurent ; et al. | 2015-10-15 |
Dual Channel Hybrid Semiconductor-on-insulator Semiconductor Devices
App 20150279861 - Cheng; Kangguo ; et al. | 2015-10-01 |
Method to prepare semi-conductor device comprising a selective etching of a silicium--germanium layer
Grant 9,076,732 - Le Tiec , et al. July 7, 2 | 2015-07-07 |
Method for producing a field effect transistor with implantation through the spacers
Grant 9,070,709 - Posseme , et al. June 30, 2 | 2015-06-30 |
Defective P-n Junction For Backgated Fully Depleted Silicon On Insulator Mosfet
App 20150179453 - CHENG; KANGGUO ; et al. | 2015-06-25 |
Dual channel hybrid semiconductor-on-insulator semiconductor devices
Grant 9,059,041 - Cheng , et al. June 16, 2 | 2015-06-16 |
Field effect transistor with offset counter-electrode contact
Grant 8,994,142 - Vinet , et al. March 31, 2 | 2015-03-31 |
Microelectronic device with isolation trenches extending under an active area
Grant 8,987,854 - Vinet , et al. March 24, 2 | 2015-03-24 |
Defective P-N junction for backgated fully depleted silicon on insulator MOSFET
Grant 8,969,966 - Cheng , et al. March 3, 2 | 2015-03-03 |
Dual Channel Hybrid Semiconductor-on-insulator Semiconductor Devices
App 20150008520 - Cheng; Kangguo ; et al. | 2015-01-08 |
Method for producing a field effect transistor with a SiGe channel by ion implantation
Grant 8,877,618 - Grenouillet , et al. November 4, 2 | 2014-11-04 |
Defective P-n Junction For Backgated Fully Depleted Silicon On Insulator Mosfet
App 20140312461 - Cheng; Kangguo ; et al. | 2014-10-23 |
Method For Manufacturing A Fin Mos Transistor
App 20140246723 - MORAND; YVES ; et al. | 2014-09-04 |
Method of producing insulation trenches in a semiconductor on insulator substrate
Grant 8,735,259 - Le Tiec , et al. May 27, 2 | 2014-05-27 |
Method for fabricating a field effect device with weak junction capacitance
Grant 8,722,499 - Vinet , et al. May 13, 2 | 2014-05-13 |
METHOD FOR PRODUCING A FIELD EFFECT TRANSISTOR WITH A SiGe CHANNEL BY ION IMPLANTATION
App 20140127871 - GRENOUILLET; Laurent ; et al. | 2014-05-08 |
Method For Producing A Field Effect Transistor With Implantation Through The Spacers
App 20140087524 - Posseme; Nicolas ; et al. | 2014-03-27 |
Microelectronic Device With Isolation Trenches Extending Under An Active Area
App 20140061798 - VINET; Maud ; et al. | 2014-03-06 |
Method For Making A Semiconductor Structure With A Buried Ground Plane
App 20130341649 - Le Tiec; Yannick ; et al. | 2013-12-26 |
Method For Treating The Surface Of A Silicon Substrate
App 20130309449 - Le Tiec; Yannick ; et al. | 2013-11-21 |
Process for assembling substrates with low-temperature heat treatments
Grant 8,530,331 - Beneyton , et al. September 10, 2 | 2013-09-10 |
Method for making a semiconductor structure with a buried ground plane
Grant 8,501,588 - Le Tiec , et al. August 6, 2 | 2013-08-06 |
Method Of Producing Insulation Trenches In A Semiconductor On Insulator Substrate
App 20130189825 - LE TIEC; Yannick ; et al. | 2013-07-25 |
Transistor And Method Of Fabrication
App 20130161746 - POSSEME; Nicolas ; et al. | 2013-06-27 |
Method To Prepare Semi-conductor Device Comprising A Selective Etching Of A Silicium-germanium Layer
App 20130109191 - LE TIEC; Yannick ; et al. | 2013-05-02 |
Field Effect Transistor With Offset Counter-electrode Contact
App 20120256262 - VINET; Maud ; et al. | 2012-10-11 |
Field Effect Device Provided With A Localized Dopant Diffusion Barrier Area And Fabrication Method
App 20120187489 - GRENOUILLET; Laurent ; et al. | 2012-07-26 |
Method For Fabricating A Field Effect Device With Weak Junction Capacitance
App 20120190214 - Vinet; Maud ; et al. | 2012-07-26 |
Process For Assembling Substrates With Low-temperature Heat Treatments
App 20120088352 - Beneyton; Remi ; et al. | 2012-04-12 |
Method For Making A Semiconductor Structure With A Buried Ground Plane
App 20110284870 - Le Tiec; Yannick ; et al. | 2011-11-24 |
Process For Assembling Substrates With Low-temperature Heat Treatments
App 20090162991 - Beneyton; Remi ; et al. | 2009-06-25 |
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