Le; Hung Qui

Patent Applications and Registrations

Patent applications and USPTO patent grants for Le; Hung Qui.The latest application filed is for "parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries".

Company Profile

2.81.52

Le; Hung Qui - Austin TX
Le; Hung Qui - Autin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Parallel Slice Processor Having A Recirculating Load-store Queue For Fast Deallocation Of Issue Queue Entries App 20210406023 - Ayub; Salma ; et al.	2021-12-30
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Grant 11,150,907 - Ayub , et al. October 19, 2	2021-10-19
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices Grant 10,983,800 - Eisen , et al. April 20, 2	2021-04-20
Linkable issue queue parallel execution slice processing method Grant 10,223,125 - Brownscheidle , et al.	2019-03-05
Processing of multiple instruction streams in a parallel slice processor Grant 10,157,064 - Eisen , et al. Dec	2018-12-18
Parallel Slice Processor Having A Recirculating Load-store Queue For Fast Deallocation Of Issue Queue Entries App 20180336036 - Ayub; Salma ; et al.	2018-11-22
Linkable Issue Queue Parallel Execution Slice Processing Method App 20180336038 - Brownscheidle; Jeffrey Carl ; et al.	2018-11-22
Linkable issue queue parallel execution slice for a processor Grant 10,133,581 - Brownscheidle , et al. November 20, 2	2018-11-20
Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entries Grant 10,133,576 - Ayub , et al. November 20, 2	2018-11-20
Reconfigurable Processor With Load-store Slices Supporting Reorder And Controlling Access To Cache Slices App 20180285118 - Eisen; Lee Evan ; et al.	2018-10-04
Reconfigurable processor with load-store slices supporting reorder and controlling access to cache slices Grant 10,083,039 - Eisen , et al. September 25, 2	2018-09-25
Reconfigurable Processor With Load-store Slices Supporting Reorder And Controlling Access To Cache Slices App 20180150300 - Eisen; Lee Evan ; et al.	2018-05-31
Reconfigurable parallel execution and load-store slice processor Grant 9,977,678 - Eisen , et al. May 22, 2	2018-05-22
Reconfigurable processing method with modes controlling the partitioning of clusters and cache slices Grant 9,971,602 - Eisen , et al. May 15, 2	2018-05-15
Parallel slice processor with dynamic instruction stream mapping Grant 9,690,585 - Eisen , et al. June 27, 2	2017-06-27
Processing of multiple instruction streams in a parallel slice processor Grant 9,690,586 - Eisen , et al. June 27, 2	2017-06-27
Processing Of Multiple Instruction Streams In A Parallel Slice Processor App 20170168837 - Eisen; Lee Evan ; et al.	2017-06-15
Processing of multiple instruction streams in a parallel slice processor Grant 9,672,043 - Eisen , et al. June 6, 2	2017-06-06
Parallel slice processor with dynamic instruction stream mapping Grant 9,665,372 - Eisen , et al. May 30, 2	2017-05-30
Reconfigurable Parallel Execution And Load-store Slice Processing Methods App 20160202991 - Eisen; Lee Evan ; et al.	2016-07-14
Reconfigurable Parallel Execution And Load-store Slice Processor App 20160202989 - Eisen; Lee Evan ; et al.	2016-07-14
Parallel Slice Processor Having A Recirculating Load-store Queue For Fast Deallocation Of Issue Queue Entries App 20160202986 - Ayub; Salma ; et al.	2016-07-14
Linkable Issue Queue Parallel Execution Slice Processing Method App 20160202992 - Brownscheidle; Jeffrey Carl ; et al.	2016-07-14
Parallel Slice Processing Method Using A Recirculating Load-store Queue For Fast Deallocation Of Issue Queue Entries App 20160202988 - Ayub; Salma ; et al.	2016-07-14
Linkable Issue Queue Parallel Execution Slice For A Processor App 20160202990 - Brownscheidle; Jeffrey Carl ; et al.	2016-07-14
Processing Of Multiple Instruction Streams In A Parallel Slice Processor App 20150324205 - Eisen; Lee Evan ; et al.	2015-11-12
Parallel Slice Processor With Dynamic Instruction Stream Mapping App 20150324204 - Eisen; Lee Evan ; et al.	2015-11-12
Parallel Slice Processor With Dynamic Instruction Stream Mapping App 20150324206 - Eisen; Lee Evan ; et al.	2015-11-12
Processing Of Multiple Instruction Streams In A Parallel Slice Processor App 20150324207 - Eisen; Lee Evan ; et al.	2015-11-12
Instruction tracking system for processors Grant 8,521,998 - Abernathy , et al. August 27, 2	2013-08-27
Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors Grant 8,418,180 - Bishop , et al. April 9, 2	2013-04-09
Multi-mode register rename mechanism that augments logical registers by switching a physical register from the register rename buffer when switching between in-order and out-of-order instruction processing in a simultaneous multi-threaded microprocessor Grant 8,347,068 - Eickemeyer , et al. January 1, 2	2013-01-01
Transactional memory system which employs thread assists using address history tables Grant 8,117,403 - Heller, Jr. , et al. February 14, 2	2012-02-14
Selecting fixed-point instructions to issue on load-store unit Grant 8,108,655 - Abernathy , et al. January 31, 2	2012-01-31
Data stream prefetching in a microprocessor Grant 7,904,661 - Fluhr , et al. March 8, 2	2011-03-08
Branch lookahead prefetch for microprocessors Grant 7,877,580 - Eickemeyer , et al. January 25, 2	2011-01-25
Processor instruction retry recovery Grant 7,827,443 - Eisen , et al. November 2, 2	2010-11-02
Selecting Fixed-Point Instructions to Issue on Load-Store Unit App 20100250901 - Abernathy; Christopher Michael ; et al.	2010-09-30
Store stream prefetching in a microprocessor Grant 7,716,427 - Griswell, Jr. , et al. May 11, 2	2010-05-11
Dynamic recalculation of resource vector at issue queue for steering of dependent instructions Grant 7,650,486 - Le , et al. January 19, 2	2010-01-19
Thread priority method for ensuring processing fairness in simultaneous multi-threading microprocessors Grant 7,631,308 - Bishop , et al. December 8, 2	2009-12-08
Using a modified value GPR to enhance lookahead prefetch Grant 7,620,799 - Eickemeyer , et al. November 17, 2	2009-11-17
Method, apparatus and program product for enhancing performance of an in-order processor with long stalls Grant 7,603,543 - Dooley , et al. October 13, 2	2009-10-13
System and method for predictive early allocation of stores in a microprocessor Grant 7,600,099 - Le , et al. October 6, 2	2009-10-06
Load lookahead prefetch for microprocessors Grant 7,594,096 - Eickemeyer , et al. September 22, 2	2009-09-22
Branch lookahead prefetch for microprocessors Grant 7,552,318 - Eickemeyer , et al. June 23, 2	2009-06-23
Data shifting through scan registers Grant 7,551,475 - Agarwal , et al. June 23, 2	2009-06-23
Store Stream Prefetching In A Microprocessor App 20090070556 - Griswell, JR.; John Barry ; et al.	2009-03-12
Processor Instruction Retry Recovery App 20090063898 - Eisen; Susan Elizabeth ; et al.	2009-03-05
Method using vector component comprising first and second bits to regulate movement of dependent instructions in a microprocessor Grant 7,490,226 - Le , et al. February 10, 2	2009-02-10
Branch encoding before instruction cache write Grant 7,487,334 - Konigsburg , et al. February 3, 2	2009-02-03
Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor Grant 7,478,276 - Bishop , et al. January 13, 2	2009-01-13
Fetch-side instruction dispatch group formation Grant 7,475,223 - Konigsburg , et al. January 6, 2	2009-01-06
Processor instruction retry recovery Grant 7,467,325 - Eisen , et al. December 16, 2	2008-12-16
Thread Priority Method for Ensuring Processing Fairness in Simultaneous Multi-Threading Microprocessors App 20080294884 - Bishop; James Wilson ; et al.	2008-11-27
Transactional Memory System Which Employs Thread Assists Using Address History Tables App 20080288730 - Heller, JR.; Thomas J. ; et al.	2008-11-20
Load lookahead prefetch for microprocessors Grant 7,444,498 - Eickemeyer , et al. October 28, 2	2008-10-28
Using a Modified Value GPR to Enhance Lookahead Prefetch App 20080250230 - Eickemeyer; Richard James ; et al.	2008-10-09
Multi-Mode Register Rename Mechanism for a Highly Threaded Simultaneous Multi-Threaded Microprocessor App 20080250226 - Eickemeyer; Richard James ; et al.	2008-10-09
Configurable Microprocessor App 20080229065 - Le; Hung Qui ; et al.	2008-09-18
Configurable Microprocessor App 20080229058 - Le; Hung Qui ; et al.	2008-09-18
System and Method for Predictive Early Allocation of Stores in a Microprocessor App 20080222395 - Le; Hung Qui ; et al.	2008-09-11
Using a modified value GPR to enhance lookahead prefetch Grant 7,421,567 - Eickemeyer , et al. September 2, 2	2008-09-02
Store stream prefetching in a microprocessor Grant 7,380,066 - Griswell, Jr. , et al. May 27, 2	2008-05-27
Data stream prefetching in a microprocessor App 20080091922 - Fluhr; Eric Jason ; et al.	2008-04-17
Branch lookahead prefetch for microprocessors App 20080091928 - Eickemeyer; Richard James ; et al.	2008-04-17
Load Lookahead Prefetch for Microprocessors App 20080077776 - Eickemeyer; Richard James ; et al.	2008-03-27
Data stream prefetching in a microprocessor Grant 7,350,029 - Fluhr , et al. March 25, 2	2008-03-25
Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue Grant 7,302,553 - Chu , et al. November 27, 2	2007-11-27
Data Shift Capability For Scannable Register App 20070240023 - Agarwal; Vikas ; et al.	2007-10-11
Instruction grouping history on fetch-side dispatch group formation Grant 7,269,715 - Le , et al. September 11, 2	2007-09-11
Method and apparatus for dynamic modification of microprocessor instruction group at dispatch Grant 7,254,697 - Bishop , et al. August 7, 2	2007-08-07
Instruction group formation and mechanism for SMT dispatch Grant 7,237,094 - Curran , et al. June 26, 2	2007-06-26
Thread priority method, apparatus, and computer program product for ensuring processing fairness in simultaneous multi-threading microprocessors App 20060184946 - Bishop; James Wilson ; et al.	2006-08-17
Lookahead mode sequencer App 20060184772 - Dooley; Miles Robert ; et al.	2006-08-17
Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processor App 20060179346 - Bishop; James Wilson ; et al.	2006-08-10
Store stream prefetching in a microprocessor App 20060179238 - Griswell; John Barry JR. ; et al.	2006-08-10
Data stream prefetching in a microprocessor App 20060179239 - Fluhr; Eric Jason ; et al.	2006-08-10
Method using hazard vector to enhance issue throughput of dependent instructions in a microprocessor App 20060179282 - Le; Hung Qui ; et al.	2006-08-10
Processor instruction retry recovery App 20060179207 - Eisen; Susan Elizabeth ; et al.	2006-08-10
Fetch-side instruction dispatch group formation App 20060174092 - Konigsburg; Brian R. ; et al.	2006-08-03
Branch encoding before instruction cache write App 20060174095 - Konigsburg; Brian R. ; et al.	2006-08-03
Instruction grouping history on fetch-side dispatch group formation App 20060174091 - Le; Hung Qui ; et al.	2006-08-03
Mechanism for self-initiated instruction issuing and method therefor Grant 7,080,241 - Le , et al. July 18, 2	2006-07-18
Load lookahead prefetch for microprocessors App 20060149935 - Eickemeyer; Richard James ; et al.	2006-07-06
Branch lookahead prefetch for microprocessors App 20060149933 - Eickemeyer; Richard James ; et al.	2006-07-06
Using a modified value GPR to enhance lookahead prefetch App 20060149934 - Eickemever; Richard James ; et al.	2006-07-06
Method for measuring memory latency in a hierarchical memory system Grant 7,051,177 - Le , et al. May 23, 2	2006-05-23
Analyzing instruction completion delays in a processor Grant 7,047,398 - Kurihara , et al. May 16, 2	2006-05-16
Instruction group formation and mechanism for SMT dispatch App 20060101241 - Curran; Brian William ; et al.	2006-05-11
Counting latencies of an instruction table flush, refill and instruction execution using a plurality of assigned counters Grant 6,970,999 - Kurihara , et al. November 29, 2	2005-11-29
Speculative counting of performance events with rewind counter Grant 6,910,120 - Le , et al. June 21, 2	2005-06-21
Method and system for efficiently restoring a processor's execution state following an interrupt caused by an interruptible instruction Grant 6,898,696 - Cheong , et al. May 24, 2	2005-05-24
Completion monitoring in a processor having multiple execution units with various latencies Grant 6,826,678 - Le , et al. November 30, 2	2004-11-30
Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue App 20040148493 - Chu, Sam Gat-Shang ; et al.	2004-07-29
Method and system for dynamically shared completion table supporting multiple threads in a processing system Grant 6,721,874 - Le , et al. April 13, 2	2004-04-13
Method and system for identifying instruction completion delays in a processor App 20040024994 - Kurihara, Toshihiko ; et al.	2004-02-05
Cycles per instruction stack in a computer processor App 20040025146 - Kurihara, Toshihiko ; et al.	2004-02-05
Speculative counting of performance events with rewind counter App 20040024996 - Le, Hung Qui ; et al.	2004-02-05
Method for measuring memory latency in a hierarchical memory system App 20040024982 - Le, Hung Qui ; et al.	2004-02-05
Determining successful completion of an instruction by comparing the number of pending instruction cycles with a number based on the number of stages in the pipeline Grant 6,658,555 - Kahle , et al. December 2, 2	2003-12-02
Mechanism to reduce instruction cache miss penalties and methods therefor Grant 6,658,534 - White , et al. December 2, 2	2003-12-02
Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling Grant 6,654,869 - Kahle , et al. November 25, 2	2003-11-25
System for rejecting and reissuing instructions after a variable delay time period Grant 6,654,876 - Le , et al. November 25, 2	2003-11-25
Completion monitoring in a processor having multiple execution units with various latencies App 20030196074 - Le, Hung Qui ; et al.	2003-10-16
Method and apparatus for patching problematic instructions in a microprocessor using software interrupts Grant 6,631,463 - Floyd , et al. October 7, 2	2003-10-07
System and method for managing the execution of instruction groups having multiple executable instructions Grant 6,553,480 - Cheong , et al. April 22, 2	2003-04-22
Content addressable storage apparatus and register mapper architecture Grant 6,480,931 - Buti , et al. November 12, 2	2002-11-12
Method and apparatus for fast operand access stage in a CPU design using a cache-like structure App 20020124157 - Le, Hung Qui ; et al.	2002-09-05
Compressed string and multiple generation engine Grant 6,442,675 - Derrick , et al. August 27, 2	2002-08-27
Method and apparatus for software-based dispatch stall mechanism for scoreboarded IOPs Grant 6,345,356 - Derrick , et al. February 5, 2	2002-02-05
System and method for executing store instructions Grant 6,336,183 - Le , et al. January 1, 2	2002-01-01
System and method for dispatching groups of instructions using pipelined register renaming Grant 6,324,640 - Le , et al. November 27, 2	2001-11-27
Mechanism for self-initiated instruction issuing and method therefor App 20010042192 - Le, Hung Qui ; et al.	2001-11-15
Mechanism for self-initiated instruction issuing and method therefor Grant 6,308,260 - Le , et al. October 23, 2	2001-10-23
Methods and apparatus for exploiting virtual buffers to increase instruction parallelism in a pipelined processor Grant 6,298,435 - Chan , et al. October 2, 2	2001-10-02
Queuing method and apparatus for facilitating the rejection of sequential instructions in a processor Grant 6,237,081 - Le , et al. May 22, 2	2001-05-22
Apparatus and method for fast unified interrupt recovery and branch recovery in processors supporting out-of-order execution Grant 6,098,167 - Cheong , et al. August 1, 2	2000-08-01
Data processing system and method for capturing history buffer data Grant 6,070,235 - Cheong , et al. May 30, 2	2000-05-30
Apparatus and method for reducing the number of rename registers required in the operation of a processor Grant 6,061,777 - Cheong , et al. May 9, 2	2000-05-09
Concurrent execution of machine context synchronization operations and non-interruptible instructions Grant 5,996,085 - Cheong , et al. November 30, 1	1999-11-30
Dispatching instructions in a processor supporting out-of-order execution Grant 5,913,048 - Cheong , et al. June 15, 1	1999-06-15
Issuing instructions in a processor supporting out-of-order execution Grant 5,887,161 - Cheong , et al. March 23, 1	1999-03-23
Data processing system and method for completing out-of-order instructions Grant 5,875,326 - Cheong , et al. February 23, 1	1999-02-23
Method and apparatus for completion of non-interruptible instructions before the instruction is dispatched Grant 5,870,582 - Cheong , et al. February 9, 1	1999-02-09
Instruction dispatch unit and method for dynamically classifying and issuing instructions to execution units with non-uniform forwarding Grant 5,864,341 - Hicks , et al. January 26, 1	1999-01-26
Method and system for reducing average branch resolution time and effective misprediction penalty in a processor Grant 5,805,876 - Bose , et al. September 8, 1	1998-09-08
Method and apparatus for writing information to registers in a data processing system using a number of registers for processing instructions Grant 5,805,906 - Cheong , et al. September 8, 1	1998-09-08
Data processing system and method for using an unique identifier to maintain an age relationship between executing instructions Grant 5,805,849 - Jordan , et al. September 8, 1	1998-09-08
Instruction dispatch unit and method for mapping a sending order of operations to a receiving order Grant 5,774,712 - Cheong , et al. June 30, 1	1998-06-30
Apparatus and method for selecting entries from an array Grant 5,754,885 - Cheong , et al. May 19, 1	1998-05-19