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Le; Binh Quang Patent Filings

Le; Binh Quang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Le; Binh Quang.The latest application filed is for "circuit and method for programming resistive memory cells".

Company Profile
1.32.5
  • Le; Binh Quang - San Jose CA
  • Le; Binh Quang - Mountain View CA
  • Le; Binh Quang - Santa Clara CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Circuit and method for programming resistive memory cells
Grant 11,217,307 - Vianello , et al. January 4, 2
2022-01-04
Circuit And Method For Programming Resistive Memory Cells
App 20210035638 - VIANELLO; Elisa ;   et al.
2021-02-04
High performance flash memory device capable of high density data storage
Grant 7,443,732 - Kuo , et al. October 28, 2
2008-10-28
High performance flash memory device capable of high density data storage
App 20070064464 - Kuo; Tiao-Hua ;   et al.
2007-03-22
Method and system for defining a redundancy window around a particular column in a memory array
Grant 7,076,703 - Le , et al. July 11, 2
2006-07-11
Method to obtain temperature independent program threshold voltage distribution using temperature dependent voltage reference
Grant 6,944,057 - Runnion , et al. September 13, 2
2005-09-13
Fast bandgap reference circuit for use in a low power supply A/D booster
Grant 6,894,473 - Le , et al. May 17, 2
2005-05-17
Fast, Accurate And Low Power Supply Voltage Booster Using A/d Converter
App 20040196093 - Le, Binh Quang ;   et al.
2004-10-07
Fast, accurate and low power supply voltage booster using A/D converter
Grant 6,798,275 - Le , et al. September 28, 2
2004-09-28
Non-volatile memory read circuit with end of life simulation
Grant 6,791,880 - Kurihara , et al. September 14, 2
2004-09-14
Buffer driver circuit for producing a fast, stable, and accurate reference voltage
Grant 6,781,417 - Le , et al. August 24, 2
2004-08-24
Circuit for fast and accurate memory read operations
Grant 6,744,674 - Le , et al. June 1, 2
2004-06-01
Method for fabricating nitride memory cells using a floating gate fabrication process
Grant 6,743,677 - Randolph , et al. June 1, 2
2004-06-01
Refresh scheme for dynamic page programming
Grant 6,700,815 - Le , et al. March 2, 2
2004-03-02
Algorithm dynamic reference programming
Grant 6,690,602 - Le , et al. February 10, 2
2004-02-10
Stepped pre-erase voltages for mirrorbit erase
App 20030218913 - Le, Binh Quang ;   et al.
2003-11-27
Method for improving read margin in a flash memory device
Grant 6,643,177 - Le , et al. November 4, 2
2003-11-04
Refresh scheme for dynamic page programming
App 20030189843 - Le, Binh Quang ;   et al.
2003-10-09
Method and apparatus for adjusting on-chip current reference for EEPROM sensing
Grant 6,525,966 - Hollmer , et al. February 25, 2
2003-02-25
Register driven means to control programming voltages
Grant 6,304,487 - Pawletko , et al. October 16, 2
2001-10-16
System for programming memory cells
Grant 6,295,228 - Pawletko , et al. September 25, 2
2001-09-25
Method and apparatus for continuously regulating a charge pump output voltage using a capacitor divider
Grant 6,288,951 - Chen , et al. September 11, 2
2001-09-11
Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device
Grant 6,275,424 - Le , et al. August 14, 2
2001-08-14
Capacitor for use in a capacitor divider that has a floating gate transistor as a corresponding capacitor
Grant 6,262,469 - Le , et al. July 17, 2
2001-07-17
Reduction of voltage stress across a gate oxide and across a junction within a high voltage transistor of an erasable memory device
Grant 6,240,017 - Le , et al. May 29, 2
2001-05-29
Method of erasing floating gate capacitor used in voltage regulator
Grant 6,072,725 - Le , et al. June 6, 2
2000-06-06
Methods and apparatus to perform high voltage electrical rule check of MOS circuit design
Grant 6,055,366 - Le , et al. April 25, 2
2000-04-25
Dual source side polysilicon select gate structure and programming method utilizing single tunnel oxide for NAND array flash memory
Grant 5,999,452 - Chen , et al. December 7, 1
1999-12-07
Scheme for page erase and erase verify in a non-volatile memory array
Grant 5,995,417 - Chen , et al. November 30, 1
1999-11-30
Charge pump circuit architecture
Grant 5,973,546 - Le , et al. October 26, 1
1999-10-26
Fast high voltage NMOS pass gate for integrated circuit with high voltage generator
Grant 5,939,928 - Le , et al. August 17, 1
1999-08-17
Dual source side polysilicon select gate structure utilizing single tunnel oxide for NAND array flash memory
Grant 5,912,489 - Chen , et al. June 15, 1
1999-06-15
High voltage NMOS pass gate having supply range, area, and speed advantages
Grant 5,909,396 - Le , et al. June 1, 1
1999-06-01
High voltage NMOS pass gate for integrated circuit with high voltage generator and flash non-volatile memory device having the pass gate
Grant 5,852,576 - Le , et al. December 22, 1
1998-12-22
High voltage NMOS pass gate having supply range, area, and speed advantages
Grant 5,844,840 - Le , et al. December 1, 1
1998-12-01
Charge pump circuit having non-uniform stage capacitance for providing increased rise time and reduced area
Grant 5,818,288 - Le , et al. October 6, 1
1998-10-06
High voltage NMOS pass gate for integrated circuit with high voltage generator
Grant 5,801,579 - Le , et al. September 1, 1
1998-09-01

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